Multi-Mode Memory Card Terminal Layout for SD and PCIe
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Solution Overview
Problem
As storage capacity increases in memory cards, the data transfer time also increases, necessitating higher-speed communication interfaces to maintain efficiency.
Innovation Solution
The memory card is designed with distinct terminal groups for single-ended and differential signal assignments, allowing it to support multiple communication standards like SD and PCIe, with differential signals assigned to separate rows to facilitate multi-lane configurations and improve data transfer speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If storage capacity is increased, then data transfer volume increases, but data transfer time increases
Solution Approach 1:
The patent changes the communication interface parameters by supporting multiple communication standards (SD and PCIe) with different speed characteristics. By detecting the host device type and selecting the appropriate communication mode, the system optimizes data transfer speed according to the storage capacity requirements, thereby reducing data transfer time for high-capacity cards.
Solution Approach 2:
The memory card dynamically switches between different communication modes (SD mode and PCIe mode) based on the detected host device type. This dynamic adaptation allows the system to optimize data transfer performance by selecting the most suitable communication interface for each scenario, effectively reducing transfer time for high-capacity storage.
2Speed
If higher-speed communication interface is used, then data transfer speed increases, but device complexity increases
Solution Approach 1:
The memory card incorporates multiple communication interfaces (SD and PCIe) within a single device, making it universal and compatible with different host devices. The card can detect the host type and automatically select the appropriate communication mode, providing high-speed transfer when needed while maintaining simplicity for standard operations.
Solution Approach 2:
The system dynamically selects between SD mode and PCIe mode based on the detected host device type. This dynamic switching mechanism allows the card to present a simplified interface to the host while internally utilizing the most appropriate communication protocol, thus achieving high speed without exposing complexity to the user.
3Adaptability or versatility
If multiple communication standards are supported, then adaptability increases, but terminal group configuration complexity increases
Solution Approach 1:
The patent segments the terminal groups into distinct rows: a first row for SD mode communication and a second row for PCIe mode communication. This segmentation allows each communication standard to have dedicated terminals, simplifying the configuration and reducing interference between different communication modes while maintaining support for both standards.
Solution Approach 2:
Different rows of terminal groups are assigned different signal types according to local requirements: the first row uses single-ended signals for SD mode, while the second row uses differential signals for PCIe mode. This local differentiation optimizes signal integrity for each communication standard and simplifies the overall configuration by assigning specific qualities to specific regions.
Data Source
AI summary
According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.