Memory Card Transfer Mode Control and Error Handling

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Solution Overview

Problem

Semiconductor memory devices face complexity and increased size due to the need for multiple transfer modes to support high data transfer rates, which can result in errors and increased power consumption when unsupported modes are attempted by host devices.

Innovation Solution

A semiconductor memory device with a host interface unit and a transfer mode control unit that outputs an error code when instructed to change to unsupported transfer clock modes, allowing seamless operation within supported bus width and clock modes, thereby preventing errors and maintaining efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the memory card supports multiple transfer modes to accommodate different host devices and data transfer rates, then the adaptability and user convenience are improved, but the device complexity and control strategy complexity increase

Engineering Contradiction:

Improvetransfer mode compatibilityVSAvoidcontrol strategy complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the transfer clock frequency based on the detected host device capability. The memory card controller identifies whether the host supports high-speed mode and automatically switches between normal mode (25 MHz) and high-speed mode (50 MHz) accordingly, eliminating the need for complex manual mode selection while maintaining compatibility across different host devices

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent implements preliminary action by detecting host device capabilities during the initialization phase before actual data transfer begins. The controller determines the appropriate transfer mode in advance based on host support for high-speed mode, and configures the interface accordingly beforehand, preventing mode mismatch errors without requiring complex runtime control strategies

Inventive Principle:

Principle #10Preliminary action

2Productivity

If the transfer clock frequency is increased to achieve higher data transfer rates, then the data transfer rate is improved, but the power consumption and electromagnetic interference increase

Engineering Contradiction:

Improvedata transfer rateVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by making the transfer clock frequency adjustable rather than fixed. The memory card interface dynamically switches between 25 MHz for normal mode and 50 MHz for high-speed mode depending on host capability and performance requirements. This dynamic adjustment allows the system to optimize between power consumption and data transfer rate, using higher frequency only when necessary and beneficial

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8176215B2Semiconductor memory device and control method for semiconductor memory device

Publication Date: 2012.05.08 KIOXIA CORP

AI summary

A memory card capable of connecting to a host device includes a flash memory, a host interface unit which transfers data between a host device and the memory card, and a transfer mode control unit which changes a data transfer mode based on a command from the host device. The transfer mode control unit outputs status data containing an error code to the host device if a transfer mode change command is inputted from the host device, instructing the memory card to change to a transfer mode not supported by the host interface unit of the memory card.