Semiconductor Memory Signal Path With Cascaded Inverters and Feedback
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently propagating signals during read and write operations due to manufacturing errors and signal attenuation, leading to potential signal loss and increased power consumption.
Innovation Solution
The semiconductor memory device incorporates a signal propagation circuit with a cascade configuration of inverted signal output circuits and negative feedback circuits, including a release function equipped with idle-state detection and recovery detection circuits, to enhance signal propagation speed and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional signal propagation circuit is used, then the circuit structure is simple, but signal loss increases and power consumption increases due to manufacturing errors and signal attenuation
Solution Approach 1:
The patent introduces a negative feedback circuit that feeds back the output signal to the input side. This feedback mechanism compensates for signal attenuation and manufacturing errors by continuously adjusting the signal level, thereby reducing signal loss while managing the increased circuit complexity through systematic feedback control
Solution Approach 2:
The patent employs multiple inverted signal output circuits with different drive strengths (first through fifth circuits) to dynamically adjust signal parameters. By selecting appropriate circuits based on signal requirements, the system optimizes signal propagation while compensating for attenuation and manufacturing variations
2Productivity
If signal propagation speed is increased to improve operation efficiency, then productivity improves, but power consumption increases
Solution Approach 1:
The patent uses a dynamic selection mechanism that switches between different inverted signal output circuits (first through fifth circuits) based on operational requirements. This dynamic approach allows the system to optimize for speed when needed while consuming less power during normal operations, thereby improving productivity without proportionally increasing power consumption
Solution Approach 2:
The negative feedback circuit operates periodically to maintain signal integrity, providing corrections at appropriate intervals rather than continuously. This periodic operation reduces overall power consumption while maintaining the necessary signal propagation speed for improved productivity
3Reliability
If manufacturing precision is improved to reduce signal loss, then reliability improves, but manufacturing cost and complexity increase
Solution Approach 1:
The negative feedback circuit compensates for manufacturing errors and signal attenuation by continuously monitoring and adjusting the signal level. This feedback mechanism improves signal propagation reliability without requiring extremely high manufacturing precision, as the system actively corrects deviations caused by manufacturing variations
Solution Approach 2:
The patent uses multiple inverted signal output circuits with different drive strengths to adapt to varying signal requirements. By selecting the appropriate circuit based on operational conditions, the system maintains reliable signal propagation while reducing dependence on high manufacturing precision
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal, wherein the signal propagation circuit includes: a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit; and a fifth inverted signal output circuit including an input terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.


