Vertically-Stacked Memory Cavities via Selective Etch Rates
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Solution Overview
Problem
Existing NAND architecture and fabrication methods face challenges in achieving improved vertically-stacked memory cells, particularly in ensuring uniform etching rates and cavity depths, leading to inefficiencies in memory cell formation and configuration.
Innovation Solution
The method involves forming a stack of alternating insulative and conductive levels with selectively modified etch rates, where some insulative levels etch faster or slower than others, allowing for varying cavity depths and configurations, and modifying conductive levels to achieve tailored memory cell formation, enabling the creation of vertically-stacked memory cells with differentiated characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional NAND architecture fabrication methods are used, then memory cells can be formed, but uniform etching rates and cavity depths cannot be achieved
Solution Approach 1:
The fabrication process is segmented into multiple distinct stages: forming alternating insulative and conductive levels, selective removal of insulative levels to create cavities, and separate formation of charge trapping layers. This segmentation allows each stage to be optimized independently, achieving uniform etching rates and cavity depths while managing process complexity through systematic breakdown of the fabrication sequence
Solution Approach 2:
Different insulative levels are selectively removed to create cavities with specific depths and configurations tailored to local requirements. The charge trapping layer is formed with varying thicknesses and compositions at different locations within the memory cell stack, enabling localized optimization of etching characteristics and memory cell performance
2Adaptability or versatility
If vertically-stacked memory cells are formed with differentiated characteristics, then memory cell configuration is improved, but fabrication complexity increases
Solution Approach 1:
The alternating stack of insulative and conductive levels is formed in advance before selective cavity formation. This preliminary structuring establishes a template that guides subsequent processing steps, enabling differentiated memory cell configurations to be achieved through selective modification rather than complete re-fabrication, thus managing complexity while enhancing adaptability
Solution Approach 2:
The invention utilizes parameter changes in material composition, layer thickness, and etching conditions to create memory cells with differentiated characteristics. By varying these parameters across different levels of the stack, the fabrication process achieves versatile memory cell configurations without requiring fundamentally different manufacturing approaches for each cell type
Data Source
AI summary
Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.