Memory CDR Phase Synchronization Using Odd-Edge Detection
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Solution Overview
Problem
In memory systems with up/down sampling daisy-chain type configurations, existing clock and data recovery (CDR) devices face challenges in accurately receiving and separating synchronization signals from multiplexed data signals, particularly due to the lack of distinction between consecutive data phases, leading to incorrect data reception.
Innovation Solution
A CDR device is designed to generate a clock and execute phase synchronization using a clock generation circuit and data recovery circuit, respectively, to extract data units from multiplexed signals by utilizing four-phase clocks and edge detection, focusing on initial synchronization with Odd edge information to correctly identify data transitions and synchronize with the synchronization signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If four-phase clocks are used to divide received data in time direction, then data reception speed increases, but phase synchronization accuracy deteriorates due to inability to distinguish between before and after of consecutive data
Solution Approach 1:
The patent applies preliminary action by performing initial synchronization using only Odd edge information before normal four-phase operation. This preliminary step establishes correct phase alignment by focusing on unambiguous Odd edges, preventing the phase ambiguity problem from affecting subsequent high-speed data reception.
Solution Approach 2:
The patent introduces Odd edge information as an intermediary element to resolve the phase synchronization problem. By using Odd edges as a reference that can be reliably distinguished, the system mediates between the need for high-speed four-phase operation and the requirement for accurate phase synchronization.
2Device complexity
If phase synchronization is performed without distinguishing Odd and Even edges, then device complexity reduces, but data reception reliability deteriorates due to incorrect phase alignment
Solution Approach 1:
The patent segments the edge information into Odd and Even categories, treating them differently in the synchronization process. This segmentation allows the system to use only Odd edges for initial phase synchronization, simplifying the control logic while improving reliability by avoiding the ambiguity of Even edges.
Solution Approach 2:
The patent applies partial action by using only Odd edge information for initial synchronization instead of all edge information. This selective approach reduces complexity by focusing on a subset of edges with unambiguous characteristics, while still achieving reliable phase synchronization.
Data Source
AI summary
A clock and data recovery device of a memory system receives a multiplexed data signal obtained by multiplexing a plurality of data units, each of which is to be transmitted to one of a plurality of memories for storage therein, in an area corresponding to each memory in an amplitude direction and a time direction. The clock and data recovery device includes a clock generation circuit configured to generate a clock, and a data recovery circuit configured to execute phase synchronization with respect to a synchronization signal included in the multiplexed data signal using the generated clock and to recover one of the data units from the area corresponding to one of the memories, from the multiplexed data signal.