Memory Cell Access Controller for Dual-Access Stability

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Solution Overview

Problem

Existing memory cell technologies face instability and reduced access reliability, especially during dual access operations at low voltages, due to process variations and additional potentials caused by accessing devices, leading to information loss and increased complexity in implementing different solutions for single and dual access scenarios.

Innovation Solution

A memory cell design with an activable switch and a controller that interrupts the access operation at least once during an access cycle, using a combination of activation and deactivation periods to stabilize the cell and prevent potential changes, allowing simultaneous access without compromising read current or writeability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dynamic VDD switching is implemented to prevent cell instability, then access reliability is improved, but device complexity increases due to requiring further voltage supply

Engineering Contradiction:
Improveaccess reliabilityVSAvoidvoltage supply complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the timing parameter of wordline activation by introducing periodic interruptions during the access operation. Instead of continuously activating the wordline, it is activated in periods separated by interruptions, which allows the cell potential to stabilize without requiring dynamic VDD switching. This parameter change resolves the contradiction by maintaining reliability through timing optimization rather than additional voltage supplies.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies periodic action by interrupting the wordline activation at regular intervals during the access operation. This periodic interruption allows the cell to stabilize its potential while maintaining overall access functionality. The periodic nature of the interruption pattern ensures that the cell has sufficient time to recover without completely disabling the access operation, thus improving reliability without adding complex voltage supply circuitry.

Inventive Principle:
Principle #19Periodic action

2Productivity

If access operation is continuous to maintain productivity, then access speed is improved, but cell instability increases due to potential changes

Engineering Contradiction:
Improveaccess speedVSAvoidcell stability
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The patent introduces periodic interruptions in the wordline activation during continuous access operations. These periodic pauses allow the cell potential to stabilize without completely stopping the access operation. The interruptions are timed to occur at critical moments when potential changes could cause instability, thus maintaining cell stability while preserving overall access productivity.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent maintains continuity of useful action by ensuring that access operations resume after interruptions. The interruptions are brief and strategically placed to only affect the critical stabilization period, while the overall access operation continues uninterrupted. This approach preserves productivity by minimizing the impact of stability measures on the continuous access workflow.

Inventive Principle:
Principle #20Continuity of useful action

3Adaptability or versatility

If multiple devices simultaneously access memory element to improve flexibility, then access flexibility is improved, but access reliability deteriorates due to conflicting potentials

Engineering Contradiction:
Improveaccess flexibilityVSAvoidaccess reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces the access controller as an intermediary that manages simultaneous access requests from multiple devices. The controller coordinates the activation of access transistors and timing of wordline signals to prevent conflicting potentials from occurring. By mediating between multiple access devices and the memory cell, it ensures that even during simultaneous access operations, the cell potential remains stable and reliable.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies dynamics by making the access control adaptive to simultaneous access conditions. The access controller dynamically adjusts the timing and duration of wordline activations based on the access pattern and cell state. This dynamic control allows multiple devices to access the memory element simultaneously while maintaining reliability through real-time coordination of access signals.

Inventive Principle:
Principle #15Dynamics

4Reliability

If deactivation periods are introduced to stabilize cell to improve reliability, then access reliability is improved, but access time increases

Engineering Contradiction:
Improveaccess reliabilityVSAvoidaccess time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by introducing only brief deactivation periods during the access operation, rather than complete deactivation cycles. These short interruptions are sufficient to allow cell potential stabilization without requiring long deactivation times. The partial nature of the deactivation (brief interruptions rather than full cycles) minimizes the time penalty while achieving the reliability benefit of stabilized cell potential.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS7492626B2Memory device with access controller
Publication Date: 2009.02.17 INFINEON TECHNOLOGIES AG
  • US7492626B2 patent drawing
  • US7492626B2 patent drawing
  • US7492626B2 patent drawing

AI summary

A memory comprises a bitline, an accessible memory element, an activable switch coupled between the bitline and the access node and a controller configured to activate the activable switch within a first activation period, to activate the activable switch within a second activation period and to deactivate the activable switch at least once when accessing to the accessible memory element during the same access operation.