Variable Resistive Memory Cell Activation Reduction
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Solution Overview
Problem
Existing variable resistive semiconductor memory devices require high activation current during write operations, as all cells are typically activated, even when only a subset of data bits need to be changed, leading to inefficiencies.
Innovation Solution
Implementing a status bit that represents the inversion of stored data, allowing for selective inversion and toggling of data bits based on comparisons between pre-existing and new data, thereby reducing the number of cells that need to be activated during a write operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all memory cells are activated during write operation, then data can be written to any cell, but activation current demand increases significantly
Solution Approach 1:
The patent segments the write operation into two phases: a pre-read phase that reads only the necessary data bits, and a write phase that activates only the cells containing mismatched data. This segmentation allows the system to identify and write only to the minimum necessary subset of cells, reducing activation current while maintaining full write capability.
Solution Approach 2:
The patent performs a preliminary read operation before the actual write operation to identify which data bits differ between the current and desired states. This preliminary action enables the system to pre-determine the exact subset of cells that need to be activated, avoiding unnecessary cell activations and reducing current consumption.
2Use of energy by moving object
If pre-read and comparison operations are performed to reduce cell activations, then activation current is reduced, but operation time increases due to additional steps
Solution Approach 1:
The patent merges the pre-read and comparison operations into a single integrated process that occurs during the normal read cycle. The sense amplifiers that would normally just read data are instead used to simultaneously compare the current data with the desired write data, identifying mismatches without requiring separate comparison circuitry or additional time cycles.
Solution Approach 2:
The patent maintains continuous useful action by performing the comparison operation during the existing read cycle rather than adding a separate preliminary step. The read operation serves dual purposes: retrieving the current data state and enabling comparison with the desired state, thus eliminating idle time and maintaining operational continuity.
Data Source
AI summary
Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.