3D Memory Cell Array Structure for Chip Size Reduction
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Solution Overview
Problem
The existing semiconductor memory devices with three-dimensional memory cell arrays face challenges in reducing chip size due to the formation of surplus portions during the manufacturing process, which increases the chip size and complicates lithography due to step differences in the stepped structure.
Innovation Solution
The proposed solution involves a memory cell array structure with a stacked body having a stopper layer and conductive layers stacked alternately, where the surplus portions are reduced by creating a gap between the outer peripheral portions, allowing for a smaller arrangement region and enabling the placement of peripheral circuits or wiring lines, thereby reducing the chip size. This is achieved through a production method using a hard mask and a substantially H-shaped resist, which separates the contact and surplus portions, allowing for a more compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory cell array structure is adopted to increase capacity, then storage density is improved, but chip size increases due to surplus portions formed during manufacturing
Solution Approach 1:
The memory cell array is divided into multiple stacked layers (first stacked body and second stacked body) with different orientations. The first stacked body extends in the first direction while the second stacked body extends in the second direction, allowing independent optimization of each segment's layout to reduce overall chip area while maintaining high storage capacity.
Solution Approach 2:
The patent transitions from a planar two-dimensional memory cell arrangement to a three-dimensional stacked structure. By stacking multiple memory cell arrays vertically and orienting them in different directions, the design achieves higher storage density without proportionally increasing the chip footprint, effectively utilizing the third dimension (vertical stacking) to resolve the area-capacity contradiction.
2Device complexity
If a stepped structure is formed during manufacturing, then three-dimensional memory cell array is created, but lithography becomes complicated due to step differences
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming the first stacked body, then forming the second stacked body with different orientation. This segmentation allows each stacking operation to be performed independently with simpler lithography patterns, avoiding the need for complex single-step lithography that would be required to create the entire three-dimensional structure at once.
Solution Approach 2:
The first stacked body is formed as a preliminary structure before creating the second stacked body. This preliminary action establishes a foundation that guides subsequent manufacturing steps, allowing the second stacked body to be aligned and integrated more easily. The step-by-step construction simplifies lithography by breaking down the complex three-dimensional patterning into manageable sequential operations.
3Ease of manufacture
If surplus portions are formed to accommodate manufacturing processes, then manufacturing is enabled, but chip size increases and peripheral circuits cannot be placed
Solution Approach 1:
The chip area is segmented into the memory cell array region and the peripheral circuit region. By orienting the first and second stacked bodies in different directions and optimizing their arrangement, the design minimizes the space required for the memory structure, thereby reducing the surplus portions and maximizing the area available for peripheral circuits and other functional elements.
Solution Approach 2:
The patent optimizes geometric parameters of the stacked bodies, including their dimensions, spacing, and orientation angles. By carefully adjusting these parameters, the design achieves compact packaging that reduces unnecessary whitespace while maintaining manufacturing feasibility, thus converting non-functional surplus areas into usable chip real estate for peripheral circuits.
Data Source
AI summary
A semiconductor memory device according to an embodiment comprises a memory cell array including a stacked body and a semiconductor film, the stacked body including first layers stacked in a third direction, the semiconductor film having a side surface facing the first layers, and the semiconductor film extending in the third direction. The stacked body has a first portion and a second portion, the first portion having a first end which is an end in a first direction, and the first portion having the semiconductor film disposed therein, and a second portion being positioned on a side of the first end of the first portion, and the second portion having disposed therein a connecting line that contacts one of the first layers and extends in the third direction. The second portion has a projecting portion that projects further in the second direction than the first portion.