Memory Cell Array Unit Defect Handling via Bit Allocation
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Solution Overview
Problem
In memory cell array units with a large number of defective non-volatile memory elements, the need for a large defect position table to store address information increases, and the use of defective memory elements in least significant bits can degrade error resilience by influencing error correction codes, leading to higher failure probabilities in decoding.
Innovation Solution
A memory cell array unit that writes n−1-bit write data excluding the least significant bit into n−1-bit allocation memory cells, excluding the defective allocation memory cell, thereby avoiding the influence of defective memory elements on error correction codes and reducing the likelihood of decoding failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a defect position table is used to store address information of defective non-volatile memory elements, then defective elements can be avoided, but the table capacity becomes large when there are many defective elements
Solution Approach 1:
The patent extracts the defective memory element from the system by detecting its presence and excluding it from future write operations. The microcontroller identifies defective elements during initialization and creates a mapping that bypasses these elements, effectively removing them from the usable memory space without requiring a large table to store all defect addresses.
Solution Approach 2:
The patent introduces an intermediary mapping mechanism between the logical address space and physical memory cells. When a defective element is detected, the system creates an alternative mapping that redirects writes to healthy memory cells, using the intermediary layer to handle the defect without needing to explicitly store every defect location.
2Object-affected harmful factors
If a defective non-volatile memory element is allocated to an LSB to reduce its influence, then the defective element is less critical, but error correction code decoding fails more frequently
Solution Approach 1:
The patent converts the harmful effect of defective memory elements into a benefit by using them as sacrificial elements that can absorb errors. By intentionally allocating defective elements to LSB positions and using them as error sinks, the system protects more critical MSB data, turning the defect into a protective mechanism for overall data integrity.
Solution Approach 2:
Instead of trying to hide or eliminate the influence of defective elements, the patent inverts the approach by deliberately placing them in LSB positions where their influence is minimized. This inversion strategy accepts the defect's presence and exploits its position to protect more significant data bits, reversing the conventional wisdom of avoiding all defects uniformly.
3Reliability
If n−1-bit write data excluding LSB is written into n−1-bit allocation memory cells excluding defective cells, then decoding failure probability is reduced, but the write operation becomes more complex
Solution Approach 1:
The patent performs preliminary detection and mapping of defective memory elements during initialization before actual data writing begins. By pre-identifying defective cells and creating an exclusion map in advance, the system simplifies subsequent write operations, as the microcontroller can directly bypass known defective cells without complex real-time decision-making during data writes.
Data Source
AI summary
A memory cell array unit according to an embodiment of the present disclosure includes a microcontroller that performs reading and writing from and into a memory cell array using n-bit allocation memory cells on the basis of read/write control from a memory controller. When a defect is found in one of the n-bit allocation memory cells, the microcontroller writes n−1-bit write data excluding data of a least significant bit among n-bit write data into n−1-bit allocation memory cells excluding the defective allocation memory cell among the n-bit allocation memory cells.