Multi-Tier Memory Cell Array Fabrication
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Solution Overview
Problem
The fabrication of arrays of memory cells, particularly nonvolatile memory cells, faces challenges due to damage or destruction of memory cells during the etching process of insulative material between elevationally stacked tiers, which affects the integrity and functionality of the memory cells.
Innovation Solution
A method of forming an array of memory cells involving the use of multiple tiers with insulative materials deposited and etched in a specific manner to prevent damage, including the use of sacrificial masking materials and selective etching to create void spaces and planarize insulative layers, ensuring the integrity of memory cells across tiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If patterned etching of insulative material is performed during fabrication of elevationally stacked memory cell tiers, then memory cell arrays can be formed with multiple tiers, but damage or destruction of memory cells in inner tiers occurs
Solution Approach 1:
The patent applies preliminary action by forming a protective coating on the memory cells of the inner tier before performing the etching process. This protective coating is deposited in advance to prevent etchant contact with the memory cells during subsequent processing steps, thereby preserving cell integrity while enabling multi-tier fabrication
Solution Approach 2:
The patent introduces an intermediary protective coating layer between the etchant and the memory cells. This intermediary layer acts as a barrier that allows the etching process to proceed on the insulative material without directly damaging the underlying memory cells, thus resolving the conflict between fabrication capability and cell protection
Data Source
AI summary
A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material. An elevationally outer tier of memory cells is formed to comprise spaced outer tier lower first conductive lines, spaced outer tier upper second conductive lines, and programmable material of individual outer tier memory cells elevationally between the outer tier first lines and the outer tier second lines where such cross. Arrays of memory cells independent of method of manufacture are disclosed.