Memory Cell Array Gate Width Expansion
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Solution Overview
Problem
Current memory cell designs face challenges in increasing transistor currents, particularly read currents, as the minimum feature size decreases, making it difficult to precisely define lines and ensure adequate spacing, especially in sub-22 nm VLSI Circuits CMOS technologies, where patterning complexities restrict the spatial dimensions of diffusion regions.
Innovation Solution
The formation of a memory cell array with poly lines inclined at an angle greater than 5° to 60° relative to semiconductor lines, allowing for increased gate widths and transistor currents, which is achieved by etching semiconductor layers and forming a grid of poly lines that run over and across semiconductor lines during the manufacturing process of integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the minimum feature size is decreased to increase storage capacity, then the storage capacity increases, but the manufacturing precision deteriorates due to patterning challenges
Solution Approach 1:
The patent changes the geometric parameters of the gate electrode, specifically increasing the gate width beyond the minimum feature size constraint. This parameter change allows the gate to provide sufficient control over the channel despite the reduced minimum feature size, thereby enabling increased storage capacity while maintaining manufacturing feasibility
2Power
If the gate width is increased to increase transistor current, then the transistor current increases, but the area occupied by the gate increases
Solution Approach 1:
The patent utilizes the third dimension by forming the gate electrode as a raised structure with height. This vertical dimension allows the gate to achieve sufficient control capacity without proportionally increasing the planar area, as the enhanced control comes from the increased gate-to-channel capacitance provided by the raised structure rather than just lateral width expansion
3Quantity of substance
If the minimum feature size is decreased, then the storage capacity increases, but the device complexity increases due to processing complexity
Solution Approach 1:
The patent changes key geometric parameters including gate width and gate height to values that are more tolerant of manufacturing variations. By increasing the gate width beyond the minimum feature size and creating a raised gate structure, the design becomes less sensitive to patterning inaccuracies, thereby reducing processing complexity while maintaining high storage capacity
Data Source
AI summary
An integrated circuit is provided with a memory cell array comprising poly lines, semiconductor lines extending in a first direction and transistor devices, wherein gates of the transistor device are formed in portions of the poly lines and channels of the transistor devices are formed in the semiconductor lines and wherein at least one portion of at least one of the poly lines runs across at least one of the semiconductor lines in a second direction inclined to a direction perpendicular to the first direction at an inclination angle of more than, for example, 5° or 10°, as measured from the direction perpendicular to first direction.