Semiconductor Memory Cell Array Layout for Alignment Deviation Compensation
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Solution Overview
Problem
In semiconductor memory with large memory capacity, the miniaturization of conductive lines and the increase of storage capacity are hindered by alignment deviations in photolithography, leading to issues like disconnection and short circuits, which require careful determination of line and hole sizes and pitches.
Innovation Solution
A layout of conductive lines with a single-edge shape and larger contact holes that can shift to accommodate alignment deviations, allowing for reduced chip size and increased storage capacity while preventing disconnection and short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size and pitch of conductive lines are reduced to increase storage capacity, then the memory capacity increases, but alignment deviations in photolithography cause disconnection and short circuit issues
Solution Approach 1:
The patent changes the geometric parameters of the contact hole layout by introducing offset distances (dx, dy) from the corner of the conductive line pattern. This parameter adjustment allows the contact hole to be positioned optimally relative to the conductive lines, compensating for alignment deviations and preventing disconnection while maintaining miniaturization benefits
Solution Approach 2:
The patent预先 designs the contact hole position with offset margins (dx, dy) that create a buffer zone against alignment deviations. This beforehand cushioning ensures that even when photolithography alignment varies, the contact hole remains properly positioned to connect conductive lines without disconnection or short circuit
2Reliability
If the size of contact holes is increased to accommodate alignment deviations, then reliability improves, but chip area increases
Solution Approach 1:
The patent optimizes the contact hole size parameters (width and length) to be sufficiently large to accommodate alignment deviations but not excessively large. The specific dimensions are carefully selected to provide the minimum necessary margin for reliability while minimizing the area occupied by contact holes and connecting lines
Solution Approach 2:
The patent applies different design approaches to different regions: contact holes are made larger only where needed for reliability at critical connection points, while the majority of the chip area maintains high-density miniaturized structures. This local quality differentiation ensures reliability improvements without proportionally increasing overall chip area
3Adaptability or versatility
If connecting lines are added to connect word lines to word line driver, then functionality is achieved, but chip size increases
Solution Approach 1:
The patent merges the connecting lines with existing conductive line structures and integrates them into the overall line & space pattern. By combining multiple functions into shared structural elements, the patent achieves necessary connectivity without adding separate dedicated connecting line structures that would increase chip area
Solution Approach 2:
The patent designs conductive lines and connecting lines with universal characteristics that allow them to serve multiple functions. The same line structures are used for both signal transmission and physical connection purposes, eliminating the need for separate specialized connecting structures and reducing overall chip area
Data Source
AI summary
A semiconductor integrated circuit according to the present invention includes a cell array composed of elements, conductive lines with a pattern of a line & space arranged on the cell array, connecting lines formed upper than the conductive lines, and contact holes which connect the conductive lines to the connecting lines. One end side of the conductive lines sequentially departs from an end of the cell array when heading from one of the conductive lines to another one, the contact holes are arranged at one end side of the conductive lines, and size of the contact holes is larger than width of the conductive lines.