Memory Cell Array Unit With Selective Bit Line Connection
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Solution Overview
Problem
In existing memory cell array units, applying voltages to all memory cell arrays at the same time leads to increased charge/discharge and leakage currents, and prevents simultaneous set and reset operations due to different bias conditions, resulting in higher latency.
Innovation Solution
A memory cell array unit with a matrix arrangement of memory units, each including a global bit line and word line, a memory cell array, connection units for selecting word and bit lines, and a storage unit for address information. The bit line selection is based on address information from adjacent memory units, allowing for different bias conditions between memory units, enabling simultaneous set and reset operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If voltages are applied to all memory cell arrays at the same time under the same bias condition, then all memory cell arrays can be accessed simultaneously, but charge/discharge current and leakage current are increased
Solution Approach 1:
The memory cell array unit is divided into multiple memory cell arrays (first, second, third, and fourth memory cell arrays) that can be independently controlled. Each memory cell array has its own bit line connection configuration, allowing selective activation. When only certain memory cell arrays need to be accessed, only those specific arrays are activated rather than all arrays simultaneously, thereby reducing the overall charge/discharge current and leakage current while maintaining the required access speed for the needed data.
2Productivity
If the same global bit line is coupled to all memory cell arrays accessed at the same time, then simultaneous access is enabled, but it is not possible to selectively perform set and reset operations with different bias conditions
Solution Approach 1:
The bit line connections are segmented into different configurations. The first and second memory cell arrays are connected to the first global bit line, while the third and fourth memory cell arrays are connected to the second global bit line. This segmentation allows independent bias condition control for different pairs of memory cell arrays, enabling simultaneous set and reset operations with different bias conditions on different memory cell arrays while maintaining simultaneous access capability.
Solution Approach 2:
Different memory cell arrays are assigned different local connection qualities - specifically, different global bit line connections. The first memory cell array and second memory cell array have one connection configuration, while the third memory cell array and fourth memory cell array have another configuration. This local quality differentiation enables each memory cell array to operate under its own optimal bias condition while still allowing simultaneous access across all arrays.
3Reliability
If set operation and reset operation are performed in order, then different bias conditions can be applied, but latency is increased
Solution Approach 1:
The memory cell arrays are segmented into independent groups (first and second arrays on one global bit line, third and fourth arrays on another global bit line) that can operate simultaneously with different bias conditions. This allows a set operation on one memory cell array and a reset operation on another memory cell array to occur at the same time, dramatically reducing latency compared to sequential operations, while maintaining operation accuracy through proper bias condition control in each segmented group.
Solution Approach 2:
The system enables continuous useful action by allowing multiple operations (set and reset) to proceed simultaneously in parallel across different memory cell arrays. Instead of waiting for one operation to complete before starting the next, the segmented architecture allows both set and reset operations to be performed concurrently on different memory cell arrays, eliminating idle time and reducing overall latency while maintaining reliable operation through proper bias conditioning.
Data Source
AI summary
A memory cell array unit according to an embodiment of the present disclosure includes a plurality of memory units arranged in a matrix. Each of the memory units includes a global bit line, a global word line, a memory cell array, a first connection unit, and a second connection unit. The first connection unit selects a word line to be coupled to the global word line. The second connection unit selects a bit line to be coupled to the global bit line, on the basis of address information obtained from the plurality of adjacent memory units.