Self-Aligned Memory Cell Array With Insulating Spacer
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Solution Overview
Problem
Tightly packed memory arrays are prone to unintentional electrical shorting between the common-source contact and the word-line contact, rendering them nonfunctional due to high current densities and dense packing of memory cells.
Innovation Solution
A memory array design featuring dielectric pillars positioned on either side of the word-line contact, with an insulating spacer surrounding the contact to prevent electrical connection between the word-line and source contacts, and a method involving the formation of dielectric pillars, conductive gate material deposition, etching, and insulating spacer formation to achieve this configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If memory cells are tightly packed to increase storage density, then manufacturing precision and area utilization improve, but electrical shorting between contacts increases
Solution Approach 1:
The patent introduces an insulating spacer as an intermediary element between the word-line contact and the source contact. This spacer physically separates the two conductive regions, preventing electrical shorting while allowing the memory cells to remain tightly packed. The spacer acts as a mediator that maintains electrical isolation without requiring increased spacing between functional elements.
Solution Approach 2:
The patent segments the contact region by introducing dielectric pillars that divide the area around the word-line contact into distinct zones. This segmentation creates isolated regions that prevent unintended electrical connection between the source contact and word-line contact, allowing high-density packing while maintaining reliability.
2Power
If vertical access transistors are used to deliver high current to small areas, then power delivery capability improves, but susceptibility to electrical shorting increases
Solution Approach 1:
The insulating spacer serves as a protective intermediary that shields the high-current vertical access transistor regions from unintended electrical connection with the word-line contact. This allows the vertical transistors to operate at high current densities without compromising electrical isolation.
3Device complexity
If self-alignment fabrication technique is used to form structures without photo resist masking, then manufacturing complexity reduces, but electrical shorting between contacts increases
Solution Approach 1:
The self-alignment fabrication technique is used to form the insulating spacer in a self-aligned manner, where the spacer automatically positions itself relative to the word-line contact and source contact regions. This self-service approach maintains electrical isolation without requiring additional photo resist masking steps, thus reducing overall fabrication complexity while preventing shorting.
Data Source
AI summary
A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line with a spacer of electrically insulating material surrounding the gate contact. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, etching a gate contact region for the word line between the pair of pillars, forming a spacer of electrically insulating material in the gate contact region, and depositing a gate contact between the pair of pillars to be in electrical contact with the gate material such that the spacer surrounds the gate contact.