Memory Cell Layout With Full Backside Connectivity for Lower Bitline RC
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Solution Overview
Problem
As semiconductor devices shrink, the available area for forming contacts and interconnects decreases, leading to increased routing complexity and parasitic resistance and capacitance, which negatively impact manufacturing costs and performance.
Innovation Solution
The implementation of compact logic cells using full backside connectivity, which involves a memory cell design with frontside and backside interconnect layers, source/drain contacts, and gate structures, allowing for reduced cell area, lower bitline resistance, and reduced bitline capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of IC devices and components are miniaturized to advance computing power, then computing power and integration density are improved, but the available area for forming contacts and interconnects decreases, leading to increased routing complexity and parasitic resistance and capacitance
Solution Approach 1:
The patent introduces a second surface (backside) for interconnect formation, transitioning from a single-surface (frontside-only) architecture to a dual-surface architecture. This dimensional change allows interconnects to be formed on both the frontside and backside of the semiconductor substrate, effectively doubling the available interconnect real estate and reducing routing complexity on each individual surface.
Solution Approach 2:
The patent segments the interconnect routing function between frontside and backside surfaces. The frontside interconnect layer handles certain routing functions while the backside interconnect layer handles others, dividing the complex routing task into manageable segments that can be optimized independently on each surface.
2Productivity
If the size of IC devices and components are miniaturized, then integration density is improved, but parasitic resistance and capacitance of contacts and interconnects increase, negatively impacting performance
Solution Approach 1:
By adding the backside interconnect layer, the patent creates additional dimensional space for routing signals and power. This allows for shorter and more direct interconnect paths compared to forcing all routing through the limited frontside area, thereby reducing parasitic resistance and capacitance while maintaining high integration density.
Solution Approach 2:
The patent extracts certain interconnect routing functions from the congested frontside to the backside, removing problematic long routing paths and reducing the parasitic effects associated with extended interconnect lengths on the frontside.
3Ease of manufacture
If all interconnects are formed on the frontside, then manufacturing process is simpler, but available area is insufficient, leading to increased routing complexity
Solution Approach 1:
The patent utilizes the backside of the semiconductor substrate as an additional dimension for interconnect formation. This effectively doubles the available area for interconnects without increasing the physical footprint of the device, allowing for more interconnects to be formed while maintaining a relatively simple dual-sided manufacturing process.
Data Source
AI summary
In an aspect, a semiconductor memory cell comprises gate structures separated by source or drain (S/D) structures, a frontside (FS) inter-layer dielectric (FS-ILD) layer above the gate and S/D structures, FS metal zero (FM0) interconnects above the FS-ILD layer, a backside (BS) inter-layer dielectric (BS-ILD) layer below the gate and S/D structures, BS metal zero (BM0) interconnects below the BS-ILD layer, at least one FS source drain contact (FSDC) electrically connecting an FM0 interconnect to a top surface of an S/D structure, and at least one BS S/D contact (BSDC) electrically connecting a BMO interconnect to a bottom surface of an S/D structure. The semiconductor memory cell comprises NFETs and PFETs to form a cross-coupled inverter pair. For each inverter in the pair, one of VDD and VSS are provided by an FSDC and the other of VDD and VSS is provided by a BSDC.