Memory Cell Layout Using Backside Word Lines to Cut RC Loading
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the resistance of conductive lines within digital devices changes, affecting operating voltages and overall IC performance.
Innovation Solution
The solution involves configuring memory cells with a first transistor of one type and a second transistor of a different type, where the first transistor is a pass-gate transistor and the second transistor is positioned below the first transistor. This configuration supplies word line signals from both the front-side and back-side of the substrate, reducing resistance capacitance (RC) loading and enhancing speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ICs become smaller and more complex, then integration density increases, but resistance of conductive lines changes affecting operating voltages and performance
Solution Approach 1:
The patent utilizes back-side contacts and interconnects to provide additional dimensional pathways for signal and power distribution. By extending the interconnect architecture into the substrate thickness dimension and utilizing both front and back surfaces, the design reduces the impact of resistive losses in planar conductors while maintaining high integration density.
Solution Approach 2:
The patent segments the interconnect function by separating front-side and back-side contacts, allowing independent optimization of each layer. This segmentation enables distributed voltage supply points throughout the substrate, reducing voltage drops and improving operating voltage stability in high-density configurations.
2Ease of manufacture
If memory cells use traditional configuration, then manufacturing is simpler, but RC loading increases reducing speed and increasing power consumption
Solution Approach 1:
The patent reduces RC loading by utilizing vertical interconnects through the substrate and back-side contacts. This three-dimensional interconnect approach shortens the effective path length for signals and power, reducing both resistance and capacitance components of RC loading, thereby increasing memory cell operating speed while maintaining manufacturing feasibility.
Solution Approach 2:
The patent introduces intermediate voltage supply points through back-side contacts and distributed interconnect structures. These intermediaries reduce the distance charges must travel, lowering RC time constants and enabling faster memory cell operation without complicating the fundamental memory cell fabrication process.
Data Source
AI summary
A memory cell includes a first, second, third, and fourth transistor, a first and a second inverter, and a first conductor and first word line bar. The second transistor is below the first transistor, and is configured as a first pass-gate transistor. The fourth transistor is below the third transistor, and is configured as a second pass-gate transistor. The first conductor extends in a first direction, is configured to supply a first signal, is on a first metal layer above a front-side of a substrate, and is coupled to the first transistor or the third transistor. The first word line bar extends in the first direction, is configured to supply a word line bar signal, is on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate, and being coupled to the second transistor and the fourth transistor.