3D Memory Cell Barrier Patterns to Prevent Charge Transfer
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Solution Overview
Problem
The integration density of semiconductor devices is limited by the area occupied by unit memory cells, and existing technologies face challenges in enhancing operation reliability, particularly in three-dimensional stacked memory cells where charge transfer between cells can occur due to insufficient energy barriers.
Innovation Solution
A semiconductor device structure is developed with alternately stacked conductive and insulating layers, a memory layer, and barrier patterns with curved sidewalls, where the barrier patterns are formed by partial oxidation of the memory layer through the insulating layers, creating an energy barrier to prevent charge transfer between stacked memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked in three dimensions to improve integration density, then storage capacity increases, but charge transfer between cells occurs due to insufficient energy barriers
Solution Approach 1:
The patent divides the continuous memory layer into segmented barrier patterns by selectively removing portions of the memory layer to form openings. These barrier patterns are separated by the openings, creating distinct energy barrier regions that prevent charge transfer between adjacent memory cells while maintaining the three-dimensional stacked structure for high integration density
Solution Approach 2:
The patent introduces barrier patterns as intermediary structures between adjacent memory cells. These barrier patterns act as energy barriers that mediate and prevent unwanted charge transfer between cells, enabling reliable three-dimensional stacking by providing electrical isolation while maintaining structural integrity
2Reliability
If barrier patterns are formed by removing memory layer material, then charge transfer is prevented, but manufacturing complexity increases
Solution Approach 1:
The patent forms the memory layer completely first, then selectively removes portions to create the barrier patterns. This preliminary formation of the complete memory layer followed by selective removal simplifies the manufacturing process compared to attempting to form barrier patterns directly, as it allows for better process control and material utilization
Solution Approach 2:
The patent changes the physical and chemical parameters of the memory layer material by selectively removing portions to form barrier patterns. This parameter change approach (removing material rather than adding complex structures) simplifies manufacturing by using standard etching and deposition processes rather than requiring novel fabrication techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure improves integration density and reliability by preventing charge transfer between memory cells, enhancing the energy barrier in the space area between stacked cells, thereby maintaining data integrity and increasing storage capacity.
Implementation Method 1
forming first barrier patterns, without removing the second material layers, by partially oxidizing the memory layer through the second material layers
Data Source
AI summary
A method of manufacturing a semiconductor device may include forming a stack with alternately stacked first material layers and second material layers, forming an opening passing through the stack, forming a memory layer in the opening, forming a slit passing through the stack and exposing the first material layers and the second material layers, and forming first barrier patterns, without removing the second material layers, by partially oxidizing the memory layer through the second material layers.