Non-Volatile Memory Cell Biasing to Prevent Program Disturbance
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Solution Overview
Problem
Existing non-volatile memory cell array structures face issues with program disturbance in non-selected memory cells during programming, leading to erroneous programming and increased complexity in conducting line layouts due to the need for multiple driving circuits.
Innovation Solution
A novel array structure and biasing method that uses specific voltage configurations to minimize program disturbance by ensuring identical program operation voltages for memory gate terminals and employing biasing techniques that prevent band-to-band tunneling effects, thereby simplifying conducting line layouts and reducing the number of driving circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple driving circuits are used to control different voltage levels for memory gate terminals, then programming control precision is improved, but device complexity and conducting line layout complexity increase
Solution Approach 1:
The patent applies universality by making the memory gate terminal serve multiple functions: it receives both the program operation voltage and the read operation voltage through the same terminal and conducting line. This eliminates the need for separate driving circuits for different voltage levels, thereby reducing conducting line layout complexity while maintaining programming control precision through proper voltage timing and sequence control
2Manufacturing precision
If multiple driving circuits are used to provide different voltages to memory gate terminals, then programming accuracy is improved, but the size of non-volatile memory increases
Solution Approach 1:
The patent merges the functions of multiple driving circuits into a single driving circuit that can provide different voltages (program operation voltage and read operation voltage) at different times through the same memory gate terminal. This consolidation reduces the number of conducting lines and driving circuits required, thereby reducing the overall area of the non-volatile memory device while maintaining programming accuracy through controlled voltage application sequences
3Ease of manufacture
If band-to-band tunneling effects are not prevented, then manufacturing simplicity is maintained, but program disturbance in non-selected memory cells occurs
Solution Approach 1:
The patent applies parameter changes by carefully controlling the voltage levels and timing sequences during programming operations. By adjusting the program operation voltage and read operation voltage parameters and applying them in specific sequences, the patent prevents band-to-band tunneling effects that cause program disturbance in non-selected memory cells, while maintaining manufacturing simplicity through standard fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces program disturbance in non-selected memory cells, simplifies conducting line layouts, and minimizes the size of non-volatile memory by using fewer driving circuits while maintaining efficient programming of selected cells.
Implementation Method 1
The tapered channel is pinched off near the second doped region, and plural hot carriers near a pinch off point are injected into the first charge storage layer of the second gate structure
Data Source
AI summary
A non-volatile memory cell includes a select transistor and a memory transistor. The first drain/source terminal of the select transistor is connected with a first control terminal. The second drain/source terminal of the select transistor is connected with the first drain/source terminal of the memory transistor. The gate terminal of the select transistor is connected with a select gate terminal. The second drain/source terminal of the memory transistor is connected with a second control terminal. The gate terminal of the memory transistor is connected with a memory gate terminal. During a program action, the select transistor is turned on, and a tapered channel is formed in the memory transistor. The tapered channel is pinched off near the first drain/source terminal of the memory transistor, and plural hot carriers near a pinch off point are injected into the charge storage layer.