Memory Cell Bit Line Precharge Compensation for Parasitic Interference
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Cell interference in nonvolatile memory devices, caused by parasitic capacitance between memory cells, leads to errors in read operations due to variations in threshold voltage distributions, especially as integration density increases.
Innovation Solution
A memory system that compensates for cell interference by precharging the bit line to a voltage level decided based on the data of adjacent memory cells, thereby reducing errors in read operations by adjusting the precharge level according to the data stored in adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integration density of memory cells is increased, then storage capacity is improved, but cell interference increases causing read errors
Solution Approach 1:
The patent applies preliminary action by precharging the bit line to a specific voltage level before the read operation based on the data state of adjacent memory cells. This advance preparation compensates for the threshold voltage shift caused by cell interference, ensuring accurate read operations even in high-density configurations where parasitic capacitance effects are significant.
2Length of moving object
If distance between memory cells is reduced, then integration density is improved, but threshold voltage stability deteriorates due to parasitic capacitance
Solution Approach 1:
The patent employs parameter changes by dynamically adjusting the bit line precharge voltage level based on the data state of adjacent memory cells. When adjacent cells are in a programmed state (which causes threshold voltage increase due to parasitic capacitance), the bit line is precharged to a lower voltage level to compensate for the expected threshold voltage shift, thereby maintaining stable and accurate threshold voltage detection despite reduced cell spacing.
3Loss of information
If program pulses are applied to memory cells, then data storage is achieved, but threshold voltage distribution shifts due to cell interference
Solution Approach 1:
The patent implements feedback by using the data state of adjacent memory cells to determine the appropriate bit line precharge voltage level for reading a target memory cell. This feedback mechanism compensates for the threshold voltage distribution shifts caused by cell interference from programmed adjacent cells, ensuring that the read operation accurately reflects the actual data state despite the interference-induced voltage shifts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise data reading by controlling the precharge level of the bit line, minimizing errors and maintaining accurate threshold voltage distributions, even in high-density memory arrays.
Implementation Method 1
cell interference occurs is that the threshold voltage of a memory cell may be influenced by a program pulse applied to an adjacent memory cell, because of parasitic capacitance existing between the memory cells
Implementation Method 2
programs a memory cell by storing electrons in a conductive band of a floating gate using F-N (Fouler-Nordheim) tunneling in the conductive band
Data Source
AI summary
A memory includes a first memory cell, a bit line corresponding to the first memory cell, at least one second memory cell adjacent to the first memory cell, and a page buffer configured to read data of the first memory cell by precharging the bit line to a voltage level which is decided in response to data of the at least one second memory cell.