Memory Cell Bit Line Switching for Fast Data Writing
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high data writing speed and low power consumption while maintaining effective charge holding capabilities, particularly due to limitations in transistor design and parasitic capacitance.
Innovation Solution
The semiconductor device incorporates a memory cell structure with a p-channel Si transistor and an n-channel OS transistor, utilizing a switch configuration to isolate memory cells during data writing, reducing parasitic capacitance and enhancing writing speed, and employing an OS transistor with low off-state current to minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional memory cell structure is used without isolation switches, then the circuit is simpler, but the parasitic capacitance increases and data writing speed decreases
Solution Approach 1:
The patent divides the bit line into isolated segments by introducing switching transistors between adjacent memory cells. This segmentation isolates the parasitic capacitance of each memory cell, allowing faster charging and discharging during write operations without affecting neighboring cells, thereby improving data writing speed while managing circuit complexity through systematic isolation.
Solution Approach 2:
The switching transistor acts as an intermediary element between adjacent memory cells on the same bit line. By controlling the isolation state of this intermediary component, the patent enables selective connection or disconnection of memory cells, reducing parasitic capacitance coupling and enhancing writing speed when the switch is closed.
2Speed
If transistors with high current driving capability are used, then data writing speed improves, but power consumption increases
Solution Approach 1:
The patent employs dynamic control of transistor isolation states through switching transistors. During write operations, the isolation switches are closed to enable fast data transfer with high current driving capability. During idle or read operations, the switches open to isolate cells, minimizing leakage current and reducing overall power consumption, thus achieving a dynamic balance between speed and power efficiency.
3Speed
If isolation switches are added between memory cells, then parasitic capacitance is reduced and writing speed improves, but the device structure becomes more complex
Solution Approach 1:
The switching transistors introduced for isolation serve multiple functions: they isolate parasitic capacitance during writes to improve speed, enable selective cell access, and can be integrated with the existing memory cell transistor design. This multi-functionality justifies the added structural complexity by delivering compounded benefits beyond simple isolation.
4Use of energy by moving object
If oxide semiconductor transistors with low off-state current are used, then power consumption is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes oxide semiconductor material properties, specifically their ability to achieve extremely low off-state currents through controlled material composition and interface quality. By changing the semiconductor material parameter from conventional silicon to oxide semiconductor, the patent achieves ultra-low power consumption in the off-state, accepting the trade-off of more stringent manufacturing precision requirements for oxide film deposition and processing.
Data Source
AI summary
A semiconductor device excellent in writing operation is provided. In a structure where a data voltage supplied to a source line is supplied to a node of a memory cell via a bit line, a switch is provided between memory cells connected to the bit line. During a period in which the data voltage is supplied to the node of the memory cell, the switch on the bit line, which is provided between the memory cells, is off. With such a structure, parasitic capacitance of the bit line during a period in which the data voltage is supplied to the node of the memory cell can be reduced. As a result, writing of the data voltage into the memory cell can be performed fast.