Multi-Level Memory Cell Programming via Bit Line Voltage Control
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Solution Overview
Problem
Current programming methods for multi-level nonvolatile semiconductor memory devices, such as incremental step pulse programming (ISPP), take a long time due to sequential processing and verification steps, which increases program time with the number of memory cells and bits.
Innovation Solution
A method that classifies memory cells into different levels and applies specific voltage levels to bit lines, allowing for simultaneous programming of memory cells into distinct states by adjusting voltages on selected and unselected bit lines, while maintaining a constant program voltage on the word line, thereby reducing overall programming time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If incremental step pulse programming (ISPP) is used to program multi-level memory cells, then programming accuracy is improved, but program time increases significantly
Solution Approach 1:
The patent segments the programming process by dividing memory cells into different groups (first group for first level, second group for second level, third group for third level) and applies different bit line voltages to each group simultaneously. This allows parallel programming of multiple levels, resolving the contradiction by maintaining accuracy through controlled voltage differentiation while reducing total program time through simultaneous operations.
Solution Approach 2:
The patent changes the bit line voltage parameter dynamically based on the target programming level. By applying distinct voltage levels (first voltage for first level, second voltage for second level, third voltage for third level) to bit lines during a single programming operation, the system achieves accurate multi-level programming without sequential processing, thus improving both accuracy and time efficiency.
2Reliability
If sequential programming from first level to third level is performed, then programming stability is improved, but productivity decreases
Solution Approach 1:
The patent performs preliminary classification of memory cells into different groups based on their target programming levels before the actual programming operation. This preliminary organization enables simultaneous programming of all levels in a single operation, achieving both stability through controlled voltage application and high productivity through parallel processing of all memory cell groups.
Solution Approach 2:
The patent introduces dynamic voltage control where bit line voltages are adjusted according to the specific programming level required for each memory cell group. This dynamic parameter adjustment allows the system to maintain programming stability through precise voltage control while achieving high productivity through simultaneous programming of multiple levels, eliminating the need for sequential operations.
3Reliability
If verification steps are applied after each program voltage, then programming reliability is improved, but program time increases with the number of memory bits
Solution Approach 1:
The patent merges the verification process into the single programming operation by simultaneously programming multiple memory cell groups to different levels with appropriate voltages. This consolidation eliminates the need for separate verification steps after each programming stage, maintaining reliability through controlled voltage application while significantly reducing the cumulative verification time that would otherwise increase with the number of memory bits.
4Manufacturing precision
If different bit line voltages are applied for different programming levels, then programming precision is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by assigning specific voltage characteristics to specific bit line groups based on their target programming levels. Each bit line group receives a tailored voltage (first voltage for first level, second voltage for second level, third voltage for third level), enabling precise programming control for each level while maintaining overall system manageability through this localized differentiation approach.
Data Source
AI summary
A programming method comprised of: classifying memory cells to be programmed into first, second and third levels; applying a program inhibition voltage to an unselected bit line, applying a ground voltage to bit lines, which are coupled with memory cells that are to be programmed into the third level, among selected bit lines, and applying a first voltage, which is lower than the program inhibition voltage but higher than a ground voltage, to bit lines coupled with memory cells that are to be programmed into the second level, and applying a second voltage, which is lower than the program inhibition voltage but higher than the first voltage, to bit line coupled with memory cells that are to be programmed into the first level; and supplying a program voltage, which gradually increases, to a selected word line coupled with the memory cells while applying the voltages to the bit lines.