Memory Cell Routing With Front- and Back-Side Butt Contacts
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Solution Overview
Problem
As semiconductor integrated circuits become smaller and more complex, the resistance of conductive lines affects operating voltages and overall IC performance, necessitating improved routing and design to optimize memory cell structures.
Innovation Solution
The implementation of first and second butt-side contacts on the front- and back-sides of memory cells, respectively, enhances routing resources and reduces the memory cell area by simplifying conductor designs compared to traditional L-shaped approaches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional L-shaped conductor designs are used, then routing flexibility is maintained, but memory cell area increases and routing efficiency decreases
Solution Approach 1:
The patent utilizes both front-side and back-side of the memory cell substrate to place contacts, effectively adding a dimensional aspect to the routing architecture. By implementing first contacts on the front-side and second contacts on the back-side, the design transforms a two-dimensional routing problem into a three-dimensional solution, reducing in-plane conductor complexity and memory cell footprint while maintaining routing flexibility.
2Reliability
If conductor lines are made shorter to reduce resistance, then operating voltage requirements improve, but routing flexibility is constrained
Solution Approach 1:
The conductor routing is segmented into front-side conductors connected to first contacts and back-side conductors connected to second contacts. This segmentation allows each conductor segment to be optimized independently for length and resistance, while the distributed contact structure provides multiple routing paths that maintain overall flexibility.
Solution Approach 2:
By distributing contacts across both front and back sides of the substrate, the patent creates three-dimensional routing paths that can be optimized for length without constraining flexibility. Conductors can be routed directly to nearest contacts on either side of the substrate, reducing total conductor length and resistance while maintaining adaptability through multiple contact options.
Data Source
AI summary
A device includes a first, second, third, and fourth transistor and a first and second conductor. The first transistor is coupled to a first node and includes a first gate. The second transistor is coupled to the first node, the second transistor includes a second gate. The third transistor is coupled to a second node, and includes a third gate separated from the first gate in a first direction. The fourth transistor is coupled to the second node, and includes a fourth gate. The first conductor is on a first metal layer above a front-side of a substrate, and is coupled to the first gate and the second node. The second conductor is on a second metal layer below a back-side of the substrate, and is coupled to the fourth gate and the first node.