Memory Cell Data Corruption via Capacitive Leakage Current
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Solution Overview
Problem
Existing technologies are inadequate in protecting data stored in integrated circuit memories from invasive or non-invasive hardware attacks, as they either fail to prevent data access or require destructive countermeasures.
Innovation Solution
A method is provided to corrupt data stored in memory cells by coupling a capacitive structure to the floating gate of state transistors, which generates a leakage current to modify the charge stored, thereby corrupting the data upon detection of an attack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If data scrambling technique is used to conceal data, then data secrecy is improved, but data remains readable during firmware execution allowing non-invasive attacks to access it
Solution Approach 1:
The patent applies preliminary anti-action by implementing a countermeasure circuit that proactively detects invasive or non-invasive attacks and immediately corrupts the data in response. Rather than merely concealing data through scrambling, the system preemptively prepares to destroy the data upon detecting any unauthorized access attempt, thereby neutralizing the vulnerability where scrambled data could still be read during firmware execution.
2Loss of information
If conventional destruction countermeasures are implemented, then data access is prevented, but the integrated circuit structure and operation are degraded
Solution Approach 1:
The patent extracts the data corruption function from the main integrated circuit structure by implementing a separate, dedicated countermeasure circuit with capacitive structures coupled to floating gates. This extraction allows the corruption mechanism to operate independently without degrading the overall circuit structure or operation, as the capacitive discharge affects only the specific memory cells targeted for corruption while leaving the rest of the circuit intact.
3Loss of information
If conventional memory clearing procedures are used, then data is corrupted, but the process requires several clock cycles allowing attack window
Solution Approach 1:
The patent implements skipping by bypassing the conventional multi-cycle memory clearing procedure entirely. Instead, the countermeasure circuit uses capacitive structures that can discharge and corrupt data in a single clock cycle or even faster, rushing through the data destruction process before an attacking system could exploit the time window between attack detection and data corruption.
4Speed
If capacitive structure with leakage current is used to corrupt data quickly, then data protection speed is improved, but precise control of corruption timing is required to avoid false triggering
Solution Approach 1:
The patent applies feedback by implementing an attack detection circuit that continuously monitors for invasive or non-invasive attacks and provides feedback signals to control the activation of the capacitive structures. This feedback mechanism ensures that the leakage current is generated only when an actual attack is detected, preventing false triggering while maintaining the ability to corrupt data at high speed when needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents unauthorized access to data by corrupting it upon detection of an attack, without degrading the operation or structure of the integrated circuit.
Implementation Method 1
generating a leakage current between the first electrically-conductive body and the second electrically-conductive body through the dielectric body, the leakage current modifying the charge of the floating gate
Implementation Method 2
The capacitive structure allows obtaining a capacitive effect between, on the one side, the first electrically-conductive body which is at a floating potential, and, on the other side, the second electrically-conductive body
Data Source
AI summary
An integrated circuit includes a memory-cell configured to store a piece of data. The memory cell includes a state transistor having a floating gate configured to store a charge representative of the piece of data and a control gate. A capacitive structure includes a first electrically-conductive body coupled to the floating gate, a second electrically-conductive body and a dielectric body between the first and second electrically-conductive bodies. A generation circuit is configured to detect an invasive or non-invasive attack and generate in response thereto a voltage applied to the second electrically-conductive body to generate a leakage current between the first and second electrically-conductive bodies through the dielectric body. The leakage current is applied to the floating gate in order to modify the charge at the floating gate and corrupt the stored piece of data.