Semiconductor Non-Volatile Memory Cell Charge Accumulation Interference
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Solution Overview
Problem
In semiconductor non-volatile memories with multiple charge accumulation portions per memory cell, data writing operations often inadvertently alter data stored in other charge accumulation portions, leading to instability and errors.
Innovation Solution
A semiconductor non-volatile memory system that supplies power to charge accumulation portions in descending order of charge amounts to be accumulated, minimizing the impact of data writing on other portions within the same memory cell, and optionally adjusts voltage to ensure accurate data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple charge accumulation portions are provided in a memory cell to increase storage capacity, then the data storage capacity is improved, but the data stability deteriorates due to mutual interference during writing operations
Solution Approach 1:
The patent applies preliminary action by performing writing operations in a predetermined sequence based on charge amount magnitude. Before writing to multiple charge accumulation portions, the system determines the writing sequence in advance (from largest to smallest charge amount), ensuring that earlier writings do not interfere with later ones. This pre-planned sequencing prevents mutual interference and maintains data stability while enabling multi-bit storage.
Solution Approach 2:
The patent implements dynamics by making the writing sequence adaptive rather than fixed. The sequence is dynamically determined based on the actual charge amounts that need to be accumulated in each portion. By flexibly adjusting the writing order according to the specific data being stored, the system optimizes interference prevention for each writing operation while maintaining high storage capacity.
2Reliability
If sequential writing is performed to reduce word line disturbance, then the interference between adjacent memory cells is reduced, but the writing time increases
Solution Approach 1:
The patent applies partial action by selectively controlling the power supply to charge accumulation portions based on their position in the writing sequence. Not all portions receive full power simultaneously; instead, power is partially applied to specific portions at specific times according to the predetermined sequence. This reduces the overall disturbance to word lines while maintaining effective writing, thereby shortening writing time compared to fully sequential approaches.
3Productivity
If power is supplied to all charge accumulation portions simultaneously, then the writing speed is improved, but the data integrity deteriorates due to mutual interference
Solution Approach 1:
The patent applies segmentation by dividing the writing operation into distinct segments, each targeting a specific charge accumulation portion in a predetermined sequence. Instead of supplying power to all portions simultaneously, the writing process is segmented into multiple stages, with each stage dedicated to one portion. This segmentation eliminates mutual interference while maintaining efficient writing speed through parallel-ready architecture.
Solution Approach 2:
The patent uses preliminary action by pre-determining the writing sequence based on charge amount requirements before actual writing begins. The system calculates which portions need writing and in what order, then executes this pre-planned sequence. This approach maintains high productivity by avoiding re-evaluation during writing while ensuring data integrity through interference-free sequential operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses changes to data stored in one charge accumulation portion during the writing operation of another, enhancing data integrity and stability in multi-bit storage scenarios.
Implementation Method 1
a charge accumulation portion capable of accumulating charge is plurally provided; supplies power in accordance with each of data units of pluralities of bits... and causes the each data unit to be memorized by charge being accumulated at the respective charge accumulation portion in a charge amount corresponding to the data unit
Data Source
AI summary
A semiconductor non-volatile memory, a data-writing method, a semiconductor non-volatile memory fabrication method and a medium storing a data-writing program that are capable of suppressing a change, due to an operation of memorization of data to a charge accumulation portion, in data which has been memorized at another charge accumulation portion in the same memory cell. Data units which are objects of memorization are memorized to first and second charge accumulation portions of a memory cell by power being supplied in accordance with the data units and charges being accumulated at the first and second charge accumulation portions, in descending order of sizes of charge amounts that are to be accumulated.