Radiation-Hardened Memory Cell With Triple-Well Charge Isolation
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Solution Overview
Problem
Current CMOS memory cells are not adequately tolerant to high-energy particle hits, as the charge generated by ionizing radiation can upset data values, especially in smaller technology designs where node separation alone is insufficient to prevent single-event upsets, and existing hardening methods like resistive hardening degrade latch performance or require modified fabrication processes.
Innovation Solution
The implementation of a self-correcting memory cell design with a data value storage circuit and address circuit featuring series address transistors in separate wells, which isolate charge generated by ionizing radiation, ensuring that the data value is restored to its initial state even after an upset event, using a combination of PMOS and NMOS transistors in inverters and triple-well techniques to prevent charge interference between wells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard CMOS memory cell design is used, then manufacturing simplicity is maintained, but SEU tolerance is insufficient
Solution Approach 1:
The memory cell is divided into separate wells (first well and second well) that are electrically isolated from each other. Each well contains specific transistors (address transistors in one well, storage transistors in the other), segmenting the charge collection regions to prevent single ion hits from affecting the entire cell, thus improving SEU tolerance while maintaining standard CMOS manufacturing
Solution Approach 2:
Different regions of the memory cell are assigned different functions and properties: the first well is optimized for address transistor operation with appropriate doping and connectivity, while the second well is optimized for storage transistor operation. This local differentiation allows each region to be optimized for its specific function while collectively providing radiation hardness
2Reliability
If node separation is increased to prevent SEU, then SEU tolerance improves, but device area increases
Solution Approach 1:
Instead of increasing horizontal separation between nodes, the patent utilizes the vertical dimension by implementing separate wells at different depths in the semiconductor substrate. The first and second wells are formed at different vertical levels and are electrically isolated, allowing compact lateral layout while achieving charge isolation through vertical separation, thus improving SEU tolerance without significantly increasing cell area
3Reliability
If resistive hardening is applied to improve SEU tolerance, then radiation hardness improves, but latch performance degrades
Solution Approach 1:
The patent changes the fundamental parameter of charge isolation from resistive mechanisms to physical well isolation mechanisms. By using separately formed wells with appropriate doping profiles and electrical connections, charge generated in one well is physically confined and cannot affect transistors in the other well, providing SEU tolerance without introducing resistive degradation that would harm latch performance
4Ease of manufacture
If standard CMOS fabrication is used, then manufacturing ease is maintained, but radiation hardness must be improved through process modification
Solution Approach 1:
The separate well structure serves multiple functions simultaneously: it provides charge isolation for SEU tolerance, enables compact layout through vertical stacking, and can be implemented using standard CMOS fabrication processes with additional well formation steps. This multi-functionality allows the design to achieve radiation hardness without sacrificing manufacturing ease, as the well isolation technique is compatible with conventional CMOS工艺流程
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances SEU tolerance by isolating charge within individual wells, reducing the likelihood of data corruption from high-energy particles, even in smaller technology nodes, without degrading latch performance or requiring non-standard fabrication processes.
Implementation Method 1
The first address transistor well is coupled to an intermediate node between the first address transistor and the second address transistor, and the second address transistor well is coupled to a ground terminal. Exposing the memory cell to ionizing radiation creates charge in one of the first address transistor well or the second transistor well, the charge being isolated to one of the first address transistor well or the second address transistor well so as to not disturb the data value.
Data Source
AI summary
A memory cell has a data value storage circuit and a data address circuit that includes a first address transistor formed in a first address transistor well and a second address transistor formed in a second address transistor well. The first address transistor is coupled between a data node and the second address transistor, and the second address transistor is coupled between the first address transistor and the data value storage circuit. The first address transistor well is coupled to an intermediate node between the first address transistor and the second address transistor, and the second address transistor well is coupled to a ground terminal.