Semiconductor Memory Cell Structure for Charge Retention
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in maintaining data retention due to the leakage of electric charges from the electric charge accumulating layer to the semiconductor layer, leading to poor charge retention characteristics during writing and latching operations.
Innovation Solution
The semiconductor memory device incorporates a semiconductor layer with protrusions that protrude towards the electric charge accumulating layer, optimizing the electric field distribution and reducing the distance between the semiconductor layer and the electric charge accumulating layer, thereby enhancing data writing and retention characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the semiconductor layer is positioned close to the electric charge accumulating layer to enhance electric field concentration, then data writing and retention characteristics are improved, but charge leakage through the tunnel insulating layer increases
Solution Approach 1:
The semiconductor layer is designed with protrusions at specific locations (opposed to corner portions of the electric charge accumulating layer) rather than a uniform structure. This creates local variations in distance and electric field distribution, concentrating electric fields at protrusion tips while maintaining adequate insulation at other regions, thus improving data writing characteristics without excessive charge leakage.
Solution Approach 2:
The invention transitions from a planar interface between the semiconductor layer and electric charge accumulating layer to a three-dimensional structure with protrusions. This dimensional change allows the semiconductor layer to approach the charge accumulating layer at specific points (reducing distance for better electric field concentration) while maintaining larger distances at other areas (reducing charge leakage).
2Reliability
If the distance between the semiconductor layer and electric charge accumulating layer is reduced to concentrate electric fields, then fringe electric fields are enhanced for better data retention, but the uniformity of the insulating layer thickness becomes more difficult to maintain
Solution Approach 1:
The tunnel insulating layer is designed with non-uniform thickness corresponding to the protrusion structure of the semiconductor layer. The insulating layer is thinner at regions opposite the protrusions (where electric field concentration is desired) and thicker at other regions (where charge leakage prevention is needed), achieving both enhanced fringe electric fields and controlled charge leakage.
3Reliability
If protrusions are added to the semiconductor layer to concentrate electric charges, then data writing characteristics are improved, but the device structure becomes more complex
Solution Approach 1:
The protrusions of the semiconductor layer are formed in advance during the manufacturing process, before the tunnel insulating layer and electric charge accumulating layer are deposited. This preliminary structuring of the semiconductor layer allows the subsequent layers to conformally follow the protrusion geometry, achieving electric field concentration without requiring additional complex processing steps for the insulating layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves data writing characteristics and charge retention by concentrating electric fields around the protrusions, reducing the likelihood of charge leakage and maintaining stable threshold voltages, resulting in better performance compared to conventional designs.
Implementation Method 1
enhancing electric field concentration and fringe electric fields
Implementation Method 2
enhancing electric field concentration and fringe electric fields
Implementation Method 3
reducing leakage through the tunnel insulating layer
Data Source
AI summary
A semiconductor memory device includes a semiconductor layer extending in a first direction, a conductive layer opposed to the semiconductor layer in a second direction intersecting with the first direction, an electric charge accumulating layer disposed between the semiconductor layer and the conductive layer, a first insulating layer disposed between the semiconductor layer and the electric charge accumulating layer, and a second insulating layer disposed between the conductive layer and the electric charge accumulating layer. The semiconductor layer includes at least one protrusion protruding in the second direction toward the electric charge accumulating layer. A position in the first direction of the protrusion is inside with respect to corner portions at both ends in the first direction of a surface opposed to the semiconductor layer in the electric charge accumulating layer.