Memory Cell Layout With Integrated CIM Multiplication
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Solution Overview
Problem
Existing memory devices face inefficiencies in performing computing-in-memory (CIM) operations due to the need for separate multiplier circuits, which increase transistor count, chip area, and data transmission delays.
Innovation Solution
Incorporating a multiplier circuit within each memory cell of the array, reducing the number of transistors required in the computation portion and minimizing the distance between storage and computation components, thereby enhancing performance and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate multiplier circuits are used for CIM operations, then computing functionality is provided, but transistor count increases
Solution Approach 1:
The patent combines the multiplier circuit functionality directly within the memory cell structure, merging storage and computation functions into a single integrated unit. This eliminates the need for separate multiplier circuits while maintaining full CIM operational capability, thereby reducing overall transistor count without sacrificing computing functionality.
2Adaptability or versatility
If separate multiplier circuits are used for CIM operations, then computing functionality is provided, but chip area increases
Solution Approach 1:
By integrating the multiplier circuit within the memory cell, the patent merges previously separate functional blocks into a compact unified structure. This spatial integration significantly reduces the total chip area required to implement both storage and computation functions, while maintaining full CIM operational capability.
3Adaptability or versatility
If separate multiplier circuits are used for CIM operations, then computing functionality is provided, but data transmission delays increase
Solution Approach 1:
The integration of multiplier circuitry within the memory cell eliminates the physical distance that data must travel between separate storage and computation units. This spatial co-location of functions drastically reduces data transmission delays and enables faster CIM operations while maintaining full computing functionality.
4Productivity
If multiplier circuit is integrated within memory cell, then processing time is reduced, but device complexity increases
Solution Approach 1:
The patent implements a segmented approach by dividing the memory cell into distinct functional regions: storage elements for holding data and integrated multiplier circuitry for computation. This segmentation allows each component to be optimized independently while working together, achieving fast processing through close proximity without excessive overall complexity.
Solution Approach 2:
The integrated memory cell structure serves multiple functions simultaneously - it acts as both a storage unit and a computation unit. This multi-functionality enables the cell to perform both data retention and CIM operations, improving processing speed while the modular design keeps device complexity manageable through functional integration.
Data Source
AI summary
A memory macro includes a weight buffer configured to output a weight signal, a memory cell configured to store a first value of a first signal at a first storage node, and a computing-in memory (CIM) circuit configured to generate an output signal in response to the first signal and a second signal, and an output circuit configured to latch the output signal. The first signal corresponds to the weight signal. The CIM circuit includes a first transistor coupled to the memory cell, and being configured to receive at least the second signal. The CIM circuit further includes an initialization circuit coupled to the first transistor, and being configured to initialize the CIM circuit in response to a third signal.