Multi-bit Memory Cell Data Detection via Interference Mitigation
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Solution Overview
Problem
Non-volatile memory systems face challenges in accurately reading data from multi-bit memory cells due to inter-region interference between storage regions, which affects the reliability and performance, especially as memory cell density increases, leading to variations in threshold voltages and incorrect readouts.
Innovation Solution
A memory system and method that utilize a data detection module to collectively process signals from multiple storage regions, accounting for inter-region interference by generating noiseless signal estimates and determining distances to recover accurate binary representations of data, thereby mitigating interference effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased to improve storage capacity, then the quantity of stored data increases, but inter-region interference between storage regions worsens, leading to threshold voltage variations and incorrect readouts
Solution Approach 1:
The read operation is segmented into multiple distinct phases: a first read operation that reads data from a first storage region, and a second read operation that reads data from a second storage region. This temporal and operational segmentation allows the system to separately access each storage region, preventing simultaneous interference while maintaining high-density storage configuration.
Solution Approach 2:
The patent performs preliminary actions by conducting the first read operation before the second read operation. By reading from the first storage region first and using that information to adjust or compensate during the second read, the system proactively mitigates interference effects before they corrupt the final data reading, thereby maintaining reliability at high densities.
2Quantity of substance
If multi-bit memory cells are used to increase storage density, then the quantity of data per cell increases, but the difficulty of detecting and measuring individual bit values worsens due to inter-region interference
Solution Approach 1:
The detection process is divided into separate detection operations for different storage regions. Each storage region is detected independently in sequence, allowing the system to isolate and measure individual bit values without the confounding interference that would occur if all regions were detected simultaneously. This segmented approach makes multi-bit cell detection feasible despite interference effects.
Solution Approach 2:
The system uses feedback from the first read operation to inform and adjust the second read operation. The data or threshold information obtained from reading the first storage region is used to compensate for or account for interference effects when reading the second storage region, thereby improving the accuracy of bit value detection in multi-bit cells.
3Device complexity
If conventional reading methods are used in high-density memory, then device complexity remains low, but measurement precision of stored data values deteriorates due to threshold voltage variations from inter-region interference
Solution Approach 1:
The patent performs a preliminary read operation from the first storage region before conducting the main read operation from the second storage region. This preliminary action provides threshold calibration or interference characterization data that is used to correct or compensate during the subsequent measurement, thereby improving precision without requiring fundamentally complex hardware modifications.
Solution Approach 2:
The first storage region and its read operation serve as an intermediary mechanism for characterizing and compensating interference effects. By using the known or controllable first storage region as a reference, the system can mediate and correct for the interference affecting the second storage region's measurements, improving precision while maintaining relatively simple device architecture.
Data Source
AI summary
A control module for a memory system including a plurality of multi-bit memory cells. The control module includes a read module configured to receive, from a first storage region of a first memory cell of the plurality of multi-bit memory cells, a first signal, and generate a second signal based on the first signal. A signal detection module is configured to determine distances between the second signal and respective estimates of a plurality of noiseless signals associated with the first memory cell. The noiseless signals correspond to a combination of an ideal signal and an interference signal. The signal detection module is further configured to determine, from the estimates of the plurality of noiseless signals, a noiseless signal that matches most closely to the second signal. A data conversion module is configured to detect data stored in the first storage region based on the noiseless signal that matches most closely to the second signal.