Semiconductor Memory Cell with Volatile-Nonvolatile Data Shadowing
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Solution Overview
Problem
Current semiconductor memory devices either operate quickly like volatile memories but lose data when power is off, or they retain data like non-volatile memories but operate slowly. There is a need for a universal memory device that combines fast operation with data retention without increasing size significantly.
Innovation Solution
A semiconductor memory cell design featuring a substrate with alternating conductivity types, a buried layer, and a nonvolatile memory component, such as a floating gate or resistance change element, that allows data to be transferred between volatile and nonvolatile states, enabling fast operation and data retention through a shadowing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile memory devices are used, then fast operation is achieved, but data retention capability deteriorates
Solution Approach 1:
The patent combines a volatile memory device (first memory device) with a non-volatile memory device (second memory device) into a single integrated memory cell structure. The first memory device provides fast operation during powered state, while the second memory device ensures data retention during power loss. This merging resolves the contradiction by making both speed and retention capabilities coexist in one device.
Solution Approach 2:
The integrated memory device performs multiple functions: it operates as volatile memory during powered state for fast access, automatically transfers data to non-volatile memory during power loss for retention, and can restore data from non-volatile memory after power restoration. This multi-functionality allows a single device to provide both fast operation and data retention capabilities.
2Reliability
If non-volatile memory devices are used, then data retention capability is improved, but operation speed deteriorates
Solution Approach 1:
The memory device dynamically switches between volatile and non-volatile memory modes based on power availability. During powered state, it operates in volatile mode for fast access; during power loss, it automatically transitions to non-volatile mode for data retention. This dynamic behavior resolves the contradiction by adapting the memory mode to operational requirements.
Solution Approach 2:
The patent introduces an intermediary transfer mechanism that automatically moves data between the volatile first memory device and non-volatile second memory device based on power state changes. This intermediary transfer process enables the system to maintain fast operation during powered state while ensuring retention during power loss, resolving the speed-retention contradiction.
3Adaptability or versatility
If a universal memory device combining volatile and non-volatile features is created, then both fast operation and data retention are achieved, but device complexity increases
Solution Approach 1:
The patent segments the memory device into distinct first and second memory devices with different conductivity types, each performing specific functions. The first memory device handles volatile operations during powered state, while the second memory device handles non-volatile retention during power loss. This segmentation allows complex functionality to be divided into simpler, dedicated modules.
Solution Approach 2:
Different regions of the memory device have different conductivity types and functional characteristics. The first memory device region provides fast volatile storage during powered state, while the second memory device region provides retention during power loss. This local differentiation of properties enables a single device to exhibit multiple memory characteristics without requiring complete redesign.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a memory device that operates quickly like volatile memories while retaining data like non-volatile memories, with data transfer occurring in parallel, enhancing speed and efficiency by maintaining data integrity during power interruptions and restoration.
Implementation Method 1
using a resistance change element to store data in a parallel, non-algorithmic process
Data Source
AI summary
A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.