Memory Cell De-trapping Voltage Pulses for Charge Removal
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Solution Overview
Problem
Charge trapping in memory cells during writing operations can lead to ambiguous memory states, causing incorrect data storage and readout failures due to trapped electrical charges affecting the conductivity of the memory cell.
Innovation Solution
A de-trapping writing scheme is implemented, which involves providing write voltage pulses and de-trapping voltage pulses with opposite polarity to remove trapped charges, followed by verification to ensure the memory cell is in the intended state, with iterative adjustments to pulse height, width, and number of pulses until the target memory state is reached.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write voltage pulses are applied to memory cells during writing operations, then data storage capability is improved, but charge trapping occurs causing ambiguous memory states and readout failures
Solution Approach 1:
The patent applies de-trapping voltage pulses with opposite polarity to convert the harmful trapped charges into beneficial effects by removing them from the memory cell. This transforms the charge trapping problem into a solvable issue by using controlled opposite polarity pulses to extract the trapped charges, thereby restoring accurate readout capability while maintaining data storage functionality
Solution Approach 2:
The patent implements preliminary de-trapping actions before verification steps by applying de-trapping voltage pulses immediately after write operations. This preliminary removal of trapped charges prevents ambiguous memory states from forming, ensuring that subsequent readout operations can accurately detect the intended memory state without interference from trapped charges
2Measurement precision
If de-trapping voltage pulses are applied to remove trapped charges, then readout accuracy is improved, but additional writing time is required due to iterative pulse adjustments
Solution Approach 1:
The patent implements a feedback mechanism where verification steps monitor the memory cell state after applying de-trapping voltage pulses. Based on the verification results, the system iteratively adjusts the number and characteristics of de-trapping pulses, applying additional pulses only when trapped charges are detected. This feedback-driven approach optimizes writing time by avoiding unnecessary pulses while ensuring complete charge removal for accurate readout
Solution Approach 2:
The patent applies de-trapping voltage pulses in controlled iterations, starting with a base number of pulses and adding more only when verification indicates trapped charges remain. This partial action approach avoids applying excessive pulses to all memory cells uniformly, instead targeting only those that require additional de-trapping, thereby reducing overall writing time while maintaining readout accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that memory cells are substantially free of trapped charges, reducing read failures and improving data storage accuracy by ensuring the memory cell is correctly switched between states.
Implementation Method 1
providing one or more de-trapping voltage pulses at the at least one memory cell, the one or more de-trapping voltage pulses having a second polarity opposite the first polarity, wherein the one or more de-trapping voltage pulses are configured such that by means of the one or more de-trapping voltage pulses trapped electrical charges may be removed from the at least one memory cell
Data Source
AI summary
According to various aspects, a memory cell arrangement is provided, the memory cell arrangement including a control circuit configured to carry out a de-trapping writing scheme to write at least one memory cell of the memory cell arrangement into a memory state, the de-trapping writing scheme including providing one or more write voltage pulses and one or more de-trapping voltage pulses at the at least one memory cell, wherein the one or more de-trapping voltage pulses have opposite polarity with respect to the one or more write voltage pulses, and wherein one or more properties of the one or more write voltage pulses and of the one or more de-trapping voltage pulses are varied as long as the memory cell is not in the memory state.