Memory Cell Array Deep Erased State Correction
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Solution Overview
Problem
Current semiconductor memory devices face challenges in maintaining reliability due to memory cells entering a deep erased state, which can lead to deteriorated retention characteristics and operational issues.
Innovation Solution
A memory device with a program operation control unit that performs an additional program operation on memory cells with a threshold voltage lower than the erase state, ensuring they reach the standard erased state, thereby improving reliability and retention characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are erased to achieve low threshold voltage state, then data storage capability is improved, but retention characteristics deteriorate due to deep erased state
Solution Approach 1:
The patent applies preliminary action by performing an additional program operation after the main program operation to proactively correct memory cells that may enter the deep erased state. This corrective action is taken in advance before the deep erased state causes retention problems, ensuring threshold voltage remains within the acceptable range and preventing future reliability issues.
Solution Approach 2:
The patent implements feedback by monitoring the threshold voltage distribution of memory cells and using this information to determine when additional program operations are needed. The system continuously assesses the state of memory cells and adjusts the erasure and programming processes accordingly, creating a closed-loop control system that maintains threshold voltage within specified limits and prevents deep erased state conditions.
2Reliability
If additional program operation is performed on all memory cells, then reliability is improved, but operation time increases
Solution Approach 1:
The patent applies local quality by performing additional program operations only on specific memory cells that exhibit threshold voltage below the erase state, rather than uniformly treating all memory cells. The system identifies and targets only those cells in the deep erased state for additional programming, leaving other cells unaffected. This selective approach maintains reliability for problematic cells while avoiding unnecessary operation time consumption on already healthy cells.
Data Source
AI summary
The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.