Memory Cell Structure With Deep-Well Biasing for RRAM Reliability

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Solution Overview

Problem

The programming voltage of new type embedded memories, such as resistive random access memories (RRAM), cannot be effectively reduced at advanced process nodes, leading to increased area and cost, and reliability issues due to high withstand voltage requirements for selectors, which affects the efficiency and integrity of the memory cell structure.

Innovation Solution

A memory cell structure with a deep well bias technology is introduced, utilizing a substrate layer and well layers with transistors and resistive cells, where the well layers are doped to apply negative voltages, reducing the voltage applied to terminals and preventing PN forward conduction, thus ensuring the reliability of the transistor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the programming voltage of new type embedded memory is reduced, then the cost and area are reduced, but the reliability of the transistor is compromised due to high withstand voltage requirements

Engineering Contradiction:

Improvetransistor reliabilityVSAvoidprogramming voltage

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The well layer is divided into a first well layer and a second well layer, where the first well layer is embedded in the substrate layer and the second well layer is arranged between the first well layer and the substrate layer. This segmentation allows independent voltage control for each well layer, enabling the first well layer to be biased at a lower voltage for reliability while the second well layer provides isolation and protection.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The second well layer acts as an intermediary structure between the first well layer and the substrate layer. It provides electrical isolation and voltage protection, allowing the first well layer to operate at reduced programming voltages without directly exposing the transistor to high withstand voltage requirements.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

If a selector with high withstand voltage value is used, then the programming voltage can be maintained, but the area of the memory cell increases

Engineering Contradiction:

Improveprogramming voltageVSAvoidmemory cell area

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The invention changes the voltage parameters by introducing a deep well bias structure with multiple well layers. The first well layer is biased at a lower voltage (e.g., -3V to -5V) while the second well layer provides isolation. This parameter change allows the use of lower programming voltages without requiring high withstand voltage selectors, thereby reducing the memory cell area.

Inventive Principle:

Principle #35Parameter changes

3Ease of manufacture

If the programming voltage is reduced to core voltage level, then the cost and area are reduced, but the transistor cannot withstand the voltage stress

Engineering Contradiction:

Improvemanufacturing costVSAvoidtransistor voltage withstand capability

Core Design Contradiction:

Ease of manufactureVSStrength

Solution Approach 1:

The second well layer is configured beforehand as a protective cushion between the first well layer and the substrate layer. It provides voltage stress protection and electrical isolation, allowing the first well layer to operate at reduced programming voltages without exposing the transistor to excessive voltage stress that would compromise its strength.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The deep well bias technology reduces the voltage applied to memory cell terminals, preventing transistor breakdown and ensuring reliable operation while maintaining the required programming voltage, thereby improving the efficiency and reducing the area and cost of the memory cell structure.

Implementation Method 1

the well layers are doped to apply negative voltages, reducing the voltage applied to terminals and preventing PN forward conduction

Methodology Applied

Scientific EffectPN junction blocking:

Data Source

PatentUS12444463B2Memory cell structure, memory array structure, and voltage biasing method

Publication Date: 2025.10.14 INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD

AI summary

Provided are a memory cell structure, a memory array structure, and a voltage biasing method. The memory cell structure includes: a substrate layer, a well layer and a transistor. The substrate layer is configured to support the memory cell structure; the well layer is embedded in the substrate layer, an upper surface of the well layer is flush with an upper surface of the substrate layer, and a transistor is arranged on the well layer.