Non-volatile Memory Cell Density via Vertical Stacking
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Solution Overview
Problem
NAND type flash memories face limitations in enhancing uniformity, reliability, speed, and integration as they rely on transistor operations for data storage, which restricts further scaling and increases manufacturing costs due to the need for multiple lithography processes and complex wiring configurations.
Innovation Solution
A non-volatile semiconductor memory device with a configuration where word lines and bit lines intersect at different layers, allowing for improved arrangement density without increasing the number of lithography processes, using resistance change elements and rectifying elements connected in series, and resistance change films extending between these lines to function as memory cells, reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If word lines and bit lines are patterned by different lithography processes to improve arrangement density, then memory cell density increases, but manufacturing cost increases and process complexity increases
Solution Approach 1:
The patent combines the patterning of word lines and bit lines into a single lithography process by forming both line patterns simultaneously in one exposure step. This is achieved by designing the mask pattern to include both word line and bit line features, and using a single resist layer that is developed to reveal both sets of lines, thereby eliminating the need for separate lithography processes and reducing manufacturing cost
Solution Approach 2:
The patent utilizes vertical stacking of multiple wiring layers to achieve high arrangement density without requiring additional planar lithography steps. By forming word lines and bit lines in different vertical layers that intersect in three-dimensional space, the design achieves high density while maintaining a simplified two-dimensional lithography process for each layer
2Quantity of substance
If the number of wiring layers is increased to improve arrangement density, then memory cell density increases, but the number of lithography processes increases and cost reduction effect decreases
Solution Approach 1:
The patent achieves high arrangement density by transitioning from two-dimensional planar arrangement to three-dimensional vertical stacking of wiring layers. Multiple word lines and bit lines are formed in different vertical layers that intersect to create memory cells in three-dimensional space, allowing high density without proportionally increasing the number of lithography processes
Solution Approach 2:
The patent divides the wiring structure into multiple vertically stacked layers, with each layer containing a subset of word lines or bit lines. This segmentation allows the complex interconnect structure to be built incrementally through repeated application of a standardized lithography and planarization process, rather than requiring increasingly complex single-step lithography
3Reliability
If NAND type flash memories use transistor operation for data storage, then reliability is improved, but further scaling is limited and manufacturing cost increases
Solution Approach 1:
The patent extracts the data storage function from the transistor operation and relocates it to the resistance change film. The transistor is reduced to a switching element that controls current flow, while the actual data storage is performed by the variable resistance state of the resistance change film, thereby simplifying the overall cell structure and enabling further scaling
Solution Approach 2:
The patent changes the fundamental storage mechanism from threshold voltage variation in transistors to resistance change in a separate resistance change film. This parameter change allows independent optimization of the switching transistor and storage element, enabling smaller transistor dimensions and lower operating voltages while maintaining reliable data storage through resistance state changes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the arrangement density of non-volatile memory cells, reduces manufacturing costs, and improves the efficiency of patterning word and bit lines simultaneously, overcoming the limitations of traditional NAND flash memories by simplifying the lithography process and increasing the vertical arrangement of memory cells.
Implementation Method 1
a phase-change memory (PCM) element and a resistive random access memory (ReRAM) element are exemplified. Since the phase-change memory element and the resistive random access memory element operate making use of a variable resistance state of a resistance material
Data Source
AI summary
According to one embodiment, a non-volatile semiconductor memory device includes: a semiconductor substrate; a plurality of first lines; a plurality of second lines; and a plurality of non-volatile memory cells arranged at positions where the plurality of first lines intersect with the plurality of second lines, wherein each of the plurality of non-volatile memory cells includes a resistance change element and a rectifying element connected in series to the resistance change element, and a resistance change film continuously extending over the plurality of second lines is arranged between the plurality of first lines and the plurality of second lines, and the resistance change element includes a portion where the first line intersect with the second line in the resistance change film.