Memory Cell Diode Prevents Parasitic Current During Write Operations
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Solution Overview
Problem
Parasitic current during write operations in memory devices leads to write disturb, reducing the reliability and lifetime of memory cells, as voltage differences between conductive lines cause leakage currents in unselected memory cells.
Innovation Solution
Incorporating a diode coupled with the read transistor and the digit line in each memory cell, which prevents parasitic current from flowing through unselected cells during write operations by acting as a rectifying element, thereby isolating unselected memory cells from the voltage difference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If voltage is applied to conductive lines during write operations, then data can be programmed into selected memory cells, but parasitic current flows through unselected memory cells causing write disturb
Solution Approach 1:
A diode is introduced as an intermediary component between the bit line and the memory cell. This diode acts as a mediator that allows current to flow during write operations when needed, but blocks parasitic current from reaching unselected memory cells, thus protecting them from write disturb while maintaining write operation functionality
Solution Approach 2:
The diode is positioned and biased to preemptively block parasitic current before it can cause harm to unselected memory cells. By establishing this protective barrier in advance, the system prevents write disturb effects before they can degrade memory cell reliability
2Power
If voltage difference is applied between bit line and source line during write operations, then data programming is enabled, but leakage current occurs in unselected cells
Solution Approach 1:
The diode serves as a selective intermediary that permits the necessary voltage difference for write operations to exist while simultaneously blocking the harmful parasitic current path. It mediates between the power application needed for writing and the prevention of leakage current in unselected cells
3Device complexity
If conventional memory cell structure is used, then device complexity is low, but write disturb reduces lifetime
Solution Approach 1:
A diode is introduced as a protective intermediary component between the bit line and the memory cell. This diode acts as a mediator that allows current to flow during write operations when needed, but blocks parasitic current from reaching unselected memory cells, thus protecting them from write disturb while maintaining write operation functionality
Solution Approach 2:
The diode provides beforehand protection by blocking parasitic current before it can cause cumulative damage to memory cells. This preliminary protective measure cushions the memory cells against write disturb effects that would otherwise reduce device lifetime
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents parasitic current from flowing through unselected memory cells, enhancing the reliability and lifetime of memory devices by mitigating write disturb effects.
Implementation Method 1
Incorporating a diode coupled with the read transistor and the digit line in each memory cell, which prevents parasitic current from flowing through unselected cells during write operations by acting as a rectifying element
Data Source
AI summary
The present disclosure includes apparatuses, methods, and systems for preventing parasitic current during program operations in memory. An embodiment includes a sense line, an access line, and a memory cell. The memory cell includes a first transistor having a floating gate and a control gate, wherein the control gate of the first transistor is coupled to the access line, and a second transistor having a control gate, wherein the control gate of the second transistor is coupled to the access line, a first node of the second transistor is coupled to the sense line, and a second node of the second transistor is coupled to the floating gate of the first transistor. The memory cell also includes a diode, or other rectifying element, coupled to the sense line and a node of the first transistor.