Two-Terminal Memory Cell With Diode and Bi-Stable Resistors
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Solution Overview
Problem
Current non-volatile memory cell arrays face limitations in density and cost due to the use of three-terminal devices, which restrict the number of bits that can be stored in each memory cell, and multi-level memory cells often require careful tuning of single elements or use one-time-programmable antifuses, limiting rewritability.
Innovation Solution
A cross-point memory array with two-terminal memory cells utilizing two bi-stable resistive elements and a current-steering device, allowing for independent programming of each element by controlling the current flow and voltage across them, enabling multiple data bits to be stored in a single cell without analog trimming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-terminal devices are used in memory cell arrays, then device functionality is achieved, but density is limited due to requiring three wires to reach each memory cell
Solution Approach 1:
The patent extracts and removes one terminal from the traditional three-terminal device structure, reducing each memory cell to a two-terminal device. This simplification allows for fewer connection wires (two instead of three), thereby increasing the density of memory cells that can be packed into an array while maintaining the essential functionality of storing multiple bits of information.
2Quantity of substance
If multi-level memory cells are designed to store multiple bits, then density increases, but rewritability is limited due to use of one-time-programmable antifuses or requiring careful tuning of single elements
Solution Approach 1:
The patent segments the memory cell into two separate bi-stable resistive elements instead of using a single element that must be carefully tuned. Each element can be independently programmed and rewritten multiple times, providing full rewritability while still enabling multiple bits to be stored in parallel within the same cell structure.
Solution Approach 2:
The patent employs dynamic, reconfigurable bi-stable resistive elements that can switch between multiple resistance states and be rewritten multiple times. This dynamic behavior replaces static one-time-programmable antifuses, enabling both multi-level storage and full rewritability through controlled application of voltage or current pulses.
3Device complexity
If a single bi-stable resistive element is used, then device simplicity is maintained, but multiple bits cannot be stored without requiring analog trimming
Solution Approach 1:
The patent divides the storage function into two separate bi-stable resistive elements, each capable of storing one bit. This segmentation allows two bits to be stored in parallel within a single memory cell without requiring complex analog trimming, as each element operates independently with its own discrete resistance states.
Solution Approach 2:
The patent utilizes discrete parameter changes in the form of two separate bi-stable resistive elements, each switching between defined high and low resistance states. This approach replaces continuous analog trimming with discrete digital-like states, enabling reliable multi-bit storage through the combined states of the two elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution achieves high density and rewritability in memory arrays by allowing each bi-stable resistive element to be settable from a high to a low resistance value and resettable from a low to a high value, enabling four different resistance states without disturbing the other element, thus overcoming the limitations of traditional memory cell arrays.
Implementation Method 1
Each bi-stable resistive element has both a high resistance and low resistance state that can be switched with appropriate application of a suitable bias voltage and current
Implementation Method 2
An exemplary memory cell includes a vertical pillar diode in series with two different bi-stable films
Data Source
AI summary
A very dense cross-point memory array of multi-level read/write two-terminal memory cells, and methods for its programming, are described. Multiple states are achieved using two or more films that each have bi-stable resistivity states, rather than “tuning” the resistance of a single resistive element. An exemplary memory cell includes a vertical pillar diode in series with two different bi-stable resistance films. Each bi-stable resistance film has both a high resistance and low resistance state that can be switched with appropriate application of a suitable bias voltage and current. Such a cross-point array is adaptable for two-dimensional rewritable memory arrays, and also particularly well-suited for three-dimensional rewritable (3D R/W) memory arrays.