Memory Cell Data Erasure via Discharge Device
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Volatile memory devices like DRAM are vulnerable to cold-boot attacks due to delayed data erasure at lower temperatures, which can compromise security measures such as full-disk encryption.
Innovation Solution
A circuit is introduced that includes a control logic with detection logic to detect signals, a boost circuit that can be disabled, and a discharge device to accelerate leakage current associated with the access transistor of the memory cell, thereby increasing the speed of data erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard DRAM operation is used, then data retention is maintained at normal temperatures, but data erasure is delayed at lower temperatures causing security vulnerabilities
Solution Approach 1:
The patent applies preliminary action by detecting the cold-boot condition before data can be extracted by attackers. The detection logic identifies when the memory device is in a vulnerable state (low temperature, power loss occurred), and proactively activates the discharge device to accelerate data erasure before the attack can occur. This prevents the security vulnerability from materializing in the first place.
Solution Approach 2:
The patent changes the electrical parameters of the memory cell by introducing a discharge device that actively modifies the voltage state of the storage node. When activated, this device creates an additional leakage path that rapidly changes the electrical parameters (voltage, charge) of the memory cell, forcing quick data erasure regardless of temperature conditions. This parameter change approach directly addresses the temperature-dependent erasure delay problem.
2Reliability
If data erasure is accelerated using additional circuits, then security is improved, but device complexity increases
Solution Approach 1:
The patent merges the security enhancement function with existing DRAM circuitry by integrating the discharge device into the memory cell's existing structure. The discharge device is coupled to the storage node through shared circuit elements, and the detection logic utilizes existing temperature sensing capabilities. This merging approach adds security functionality while minimizing the increase in device complexity.
Solution Approach 2:
The patent implements self-service by designing the detection logic to automatically identify cold-boot conditions and trigger the discharge device without external intervention. The system monitors its own state (temperature, power status) and autonomously activates the data erasure mechanism when vulnerability is detected. This self-service approach reduces the need for additional control circuits and simplifies the overall system architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly accelerates the erasure of data in memory cells, enhancing security by rapidly removing sensitive information and preventing unauthorized access.
Implementation Method 1
a discharge device coupled to an output terminal of the boost circuit to accelerate leakage of a leakage current in response to the detection of the signal, wherein the leakage current is a leakage current associated with an access transistor of the memory cell
Data Source
AI summary
Embodiments include apparatuses, methods, and systems including a circuit which may increase a speed of removal of data stored in a memory cell. In embodiments, the circuit may include a control logic to detect a signal and a boost circuit coupled to the control logic to allow the control logic to disable an operation of the boost circuit in response to detection of the signal. A discharge device may be coupled to the boost circuit to accelerate leakage of a leakage current in response to the detection of the signal. In the embodiment, the leakage current is a leakage current of a memory cell coupled to the discharge device and acceleration of the leakage of the leakage current and the disablement of the operation of the boost circuit may increase a speed of erasure of data in the memory cell. Other embodiments may also be described and claimed.