Multi-level Memory Cell Using Discharge Time Delay for Level Definition
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Solution Overview
Problem
Current semiconductor memory cells face limitations in storing multiple bits due to the limited spectrum width of physical parameters, which affects the accuracy of programming and reading characteristic values, especially as the number of levels increases, leading to interference from electrical noise and sense voltage disturbances.
Innovation Solution
A method where the effective resistance of a memory cell is varied to represent multiple binary values, with electron discharge times corresponding to specific target times, allowing for precise storage and retrieval of binary values by matching discharge times to predetermined levels, even in the presence of noise and variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of levels in a memory cell increases to store more bits, then the storage capacity increases, but the measurement precision of the characteristic parameter deteriorates due to electrical noise and sense voltage disturbance
Solution Approach 1:
The patent changes the characteristic parameter from static (threshold voltage) to dynamic (discharge time). By measuring the time required for the memory cell to discharge from one voltage level to another, the system obtains a time-based characteristic that is less susceptible to electrical noise and sense voltage disturbances, thereby maintaining measurement precision while increasing storage capacity through multiple discharge time levels.
2Quantity of substance
If the spectrum width of physical parameter is limited, then the manufacturing precision is constrained, but the storage capacity cannot be increased further
Solution Approach 1:
The patent replaces the static electrical parameter measurement (threshold voltage) with a dynamic temporal measurement (discharge time). This substitution transforms the measurement domain from voltage-based to time-based, effectively bypassing the limitations of physical parameter spectrum width and manufacturing precision while enabling multi-level storage through distinguishable discharge time characteristics.
3Quantity of substance
If the number of bands increases for n-bit cell storage, then the storage capacity increases, but the ability to program and read characteristic parameter accurately deteriorates
Solution Approach 1:
The patent introduces dynamic behavior into the memory cell operation by utilizing discharge time as the characteristic parameter. The discharge process naturally provides distinct time profiles for different charge levels, making it easier to differentiate between multiple stored values. This dynamic approach simplifies the programming and reading operations compared to static parameter measurement, as the discharge time inherently provides clear separation between different stored states.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate storage and retrieval of multiple bits in a single memory cell by utilizing electron discharge times as characteristic parameters, enhancing the ability to program and read multiple levels while minimizing disturbances, thus improving the efficiency and accuracy of data storage.
Implementation Method 1
time required for voltage to be discharged through an electronic circuit formed, at least partially, by the memory cell
Implementation Method 2
variation of the characteristic parameter of the memory cell affects the effective resistance of the memory cell
Data Source
AI summary
A method for operating a memory cell. Memory cells represent binary values by storing a characteristic parameter. The method of memory cell operation entails receiving a binary value to be stored by a memory cell. A determining operation determines a target discharge time corresponding to the binary value. The target discharge time being the time needed to discharge a pre-charged circuit through the said memory cell to a predetermined level. A storing operation stores a characteristic parameter in the memory cell such that an electron discharge time through an electronic circuit formed, at least partially, by the memory cell, is substantially equal to the target discharge time.