Non-volatile Memory Cell Array Write Speed Uniformity Control
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Solution Overview
Problem
As non-volatile semiconductor memory capacity increases, variations in write speed occur due to voltage drops along bit lines and interdependencies between memory cell states, leading to reduced reliability and increased write time.
Innovation Solution
Implementing a switch control circuit that connects bit lines to data lines and uses switches to adjust drain voltages on a memory cell-by-memory cell basis, allowing for individual control of write speeds by changing voltage levels and supply periods based on column addresses and memory cell states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell array area is increased to increase capacity, then storage capacity is improved, but voltage drop along bit lines increases causing variations in write speed
Solution Approach 1:
The memory cell array is divided into multiple blocks, with each block having its own dedicated bit line pair. This segmentation isolates the voltage drop effects within each block, preventing cumulative voltage drops across the entire large array from affecting all memory cells uniformly, thereby maintaining write speed uniformity across the expanded capacity.
Solution Approach 2:
Selection transistors are introduced as intermediary components between the bit lines and memory cell groups. These transistors act as switching mediators that can selectively connect or disconnect specific memory cell groups from bit lines, enabling control over which cells receive write operations and allowing compensation for voltage drops by selecting cells with adequate voltage levels.
2Productivity
If simultaneous write operation is performed on multiple memory cells to reduce write time, then productivity is improved, but variations in write speed increase due to bit line voltage drops
Solution Approach 1:
The system dynamically selects which memory cell groups to write to based on real-time voltage conditions on the bit lines. By adaptively adjusting the write operation targets according to voltage drops, the system maintains uniform write speeds across simultaneously operated cells while preserving high productivity through parallel operations.
Solution Approach 2:
The write operation mechanism incorporates feedback regarding bit line voltage levels to determine which memory cell groups are suitable for writing. This feedback loop ensures that only cell groups with adequate voltage levels are selected for simultaneous write operations, preventing variations in write speed while maintaining high throughput.
3Quantity of substance
If memory cell states are interdependent to store multiple bits, then storage capacity is improved, but write speed variations increase due to state influence
Solution Approach 1:
Different write voltage conditions are applied to different memory cell groups based on their specific states and positions. By tailoring the write operation parameters to local cell group characteristics rather than applying uniform write conditions across all cells, the system handles interdependent states effectively while maintaining consistent write speeds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces variations in write speed and threshold levels, enhancing memory cell reliability and preventing increases in write time caused by speed variations.
Implementation Method 1
a portion of electrons traveling from the second impurity region 603 toward the first impurity region 602 become hot by a high electric field in the vicinity of the first impurity region 602
Implementation Method 2
electrons are locally injected into the trapping layer 605 in the vicinity of the first impurity region 602
Data Source
AI summary
When a plurality of non-volatile memory cells in a memory cell array are simultaneously written, bit lines of the plurality of non-volatile memory cells are connected to M data lines, where M is an integer of two or more, based on a column address signal. N switches, where N is an integer of one or more, and a switch control circuit for controlling the N switches, are provided for each data line. The M switch control circuits control the M×N switches to change the levels or apply periods of drain voltages applied to the bit lines of the plurality of memory cells on a memory cell-by-memory cell basis.