Memory Cell Drift Mitigation via Embedded Refresh
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Solution Overview
Problem
Access operations in memory devices can cause a shift in the threshold voltage of memory cells, leading to reduced reliability and potential data loss due to drift, which existing technologies have not effectively mitigated.
Innovation Solution
A method involving the application of write and read voltages with different polarities to memory cells, including a first read voltage with a first polarity, followed by a second read voltage with a different polarity to refresh the memory cell, and potentially additional read voltages to revert the memory cell to its original state, thereby mitigating threshold voltage shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If access operations are performed on memory cells, then data can be read and written, but threshold voltage drift occurs leading to reduced reliability
Solution Approach 1:
The patent applies a refresh operation immediately after the read operation on the same memory cell. This preliminary action counteracts the threshold voltage drift caused by the read operation before it can lead to data loss. The refresh operation restores the memory cell state to its original condition, preventing the accumulation of drift effects during subsequent operations.
Solution Approach 2:
The patent discards the harmful effect of threshold voltage drift by applying a refresh operation that recovers the original memory cell state. The refresh operation effectively discards the drifted state and recovers the intended logic state, maintaining data integrity without requiring external intervention.
2Ease of operation
If multiple read operations are performed on a memory cell, then data can be accessed, but threshold voltage shifts accumulate causing data loss
Solution Approach 1:
The patent implements a periodic refresh operation that follows each read operation. This periodic action ensures that the memory cell is restored to its original state at regular intervals, preventing the accumulation of threshold voltage shifts. The periodic refresh cycle maintains data accessibility while preventing information loss.
Solution Approach 2:
The patent uses a feedback mechanism where the result of the read operation triggers a refresh operation on the same memory cell. This feedback loop ensures that any threshold voltage shift caused by the read operation is immediately corrected, maintaining data integrity through automatic compensation.
3Reliability
If refresh operations are performed after each read, then drift is mitigated, but operation complexity increases
Solution Approach 1:
The patent merges the refresh operation with the read operation sequence by applying the refresh operation on the same memory cell immediately after the read operation. This combining of operations reduces the need for separate refresh cycles and integrates drift mitigation into the normal read/write operation flow, reducing overall system complexity.
Solution Approach 2:
The patent implements a self-service mechanism where the memory cell is automatically refreshed after being read, without requiring external control logic. The refresh operation is triggered automatically by the read operation itself, making the system self-correcting and reducing the complexity of external control circuits.
Data Source
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AI summary
Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage-a setback voltage-of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.