Memory Cell Error Detection via Dual Read Latching
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Solution Overview
Problem
Memory devices face intermittent failures due to charge degradation in cell capacitors, which are difficult to detect and correct, especially as integration increases and capacitance reduces, leading to irregular and hard-to-prevent data loss.
Innovation Solution
A memory device with error detection and correction mechanisms, including a detection unit that latches and compares data from memory cells, generates refresh and detection addresses, and uses flag signals to toggle operations for error detection and correction during refresh cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If typical refresh operation is performed on constant cycle, then memory device maintains normal operation, but intermittent failure cannot be detected or prevented
Solution Approach 1:
The error detection unit is merged with the existing refresh operation structure. The detection unit utilizes the same row address generation mechanism and memory cell access infrastructure as the refresh operation, combining error detection functionality with the existing refresh framework rather than implementing a completely separate detection system.
Solution Approach 2:
The refresh operation structure is designed to serve dual purposes: normal memory refresh and error detection. By controlling the detection unit to operate during refresh cycles and using the same address generation and memory access pathways, the system achieves multi-functionality where a single operational framework handles both maintenance and diagnostics.
2Reliability
If conventional test and repair is used for failed cells, then detected failures are repaired, but intermittent failures in non-detected cells cannot be prevented
Solution Approach 1:
The error detection operation continues continuously during normal memory refresh cycles rather than being a separate periodic test. The detection unit operates whenever refresh is performed, ensuring continuous monitoring of memory cell health without requiring additional dedicated test time or interrupting normal memory operations.
Solution Approach 2:
The memory device performs self-diagnosis by comparing current read data with previously latched data during its own refresh operations. The system uses its existing read and write capabilities to detect errors, enabling the memory device to monitor its own health without external testing equipment or separate diagnostic procedures.
3Reliability
If data is read and compared with latched data for error detection, then intermittent failures are detected, but additional read operations increase operational overhead
Solution Approach 1:
Data is latched during the first read operation before comparison occurs. This preliminary latching action stores the reference data in advance, allowing the comparison to proceed efficiently without requiring additional read operations. The latched data serves as the baseline for detecting subsequent changes or errors.
Solution Approach 2:
Error detection is performed periodically during refresh cycles rather than continuously. The detection unit compares latched data with current read data at regular intervals defined by the refresh period, achieving effective error detection while minimizing the frequency of additional read operations and associated overhead.
Data Source
AI summary
A memory device may include a plurality of memory cells; an error detection unit suitable for: latching data read a first time from at least one selected memory cell of the plurality of memory cells in a detection period, comparing data read a second time from the at least one selected memory cell with the latched data, and detecting an error of the at least one selected memory cell in the detection when the date read a second time from the at least one substantially the same with the latched data.