Nonvolatile Memory Cell With Substrate-Embedded Erase Gate
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Solution Overview
Problem
Prior art nonvolatile memory cells have insufficient erase efficiency, necessitating an improvement in this aspect for enhanced performance.
Innovation Solution
A nonvolatile memory cell design featuring a substrate with a drain region, source region, and channel region, including a floating gate, select gate, control gate, and an erase gate with a lower end portion extending into the substrate, along with a method for fabricating this structure involving the formation of a recessed region, tunnel dielectric layer, and erase gate, which enhances erase efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional nonvolatile memory cell structure is used, then the device can be manufactured with standard processes, but the erase efficiency is insufficient
Solution Approach 1:
The erase gate extends vertically into the substrate, utilizing the depth dimension to enhance erase efficiency. By positioning the lower end portion of the erase gate at a depth between 0.1-1.0 micrometers into the substrate, the patent creates a three-dimensional electric field distribution that improves hole injection and carrier sweep-out, directly addressing the insufficient erase efficiency of conventional planar structures
Solution Approach 2:
The memory cell structure employs nested gate configurations where the control gate is disposed on the floating gate, and the erase gate is positioned within the substrate beneath the source region. This nested arrangement allows multiple functional gates to occupy different spatial layers, enabling enhanced erase efficiency without proportionally increasing lateral device footprint
2Reliability
If the erase gate extends into the substrate, then erase efficiency is improved, but the fabrication process becomes more complex
Solution Approach 1:
The recessed region is formed in the substrate before depositing the tunnel dielectric layer and erase gate materials. This preliminary action of creating the recessed region (with depth of 0.1-1.0 micrometers) beforehand simplifies subsequent fabrication steps by providing a pre-defined cavity that guides the formation of the erase gate structure, making the overall process more manageable despite the added complexity
Solution Approach 2:
The tunnel dielectric layer is selectively formed in the recessed region and on the gate structure surfaces, creating localized dielectric regions with specific properties. This local quality approach allows the erase gate to have enhanced coupling with the floating gate only where needed (in the recessed region), while maintaining standard structures elsewhere, thus balancing fabrication complexity with performance improvement
Data Source
AI summary
A nonvolatile memory cell includes a substrate having a drain region, a source region, and a channel region between the drain region and the source region. A floating gate and a select gate are disposed on the channel region. A control gate is disposed on the floating gate. An erase gate is disposed on the source region. The erase gate includes a lower end portion that extends into a major surface of the substrate.