Memory Cell Error Correction via Interleaved Check Bits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional data storage devices face challenges in efficiently correcting errors in data value memory cells, particularly adjacent 2-bit errors, which require a large chip area and complex wiring, limiting their reliability and data density.
Innovation Solution
A storage device configuration that includes multiple data value memory cells and check value memory cells, where each data value memory cell is assigned to two check value memory cells, and vice versa, with a correction circuit that outputs a corrected data value based on the content of the selected data value memory cell and its associated check value memory cells, using XOR or XNOR operations to form check values and correct errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction methods are used, then error correction capability is achieved, but chip area increases and wiring complexity increases
Solution Approach 1:
The patent combines data value storage and check value storage in an integrated memory structure where check bits are interleaved with data bits. This merging approach allows error correction functionality to be achieved without requiring separate dedicated correction circuits, thereby reducing overall chip area while maintaining error correction capability.
Solution Approach 2:
The memory cells serve multiple functions: they store both data values and check values, and the same memory structure is used for both data storage and error correction purposes. This multi-functionality eliminates the need for separate correction hardware, reducing chip area while preserving reliability.
2Reliability
If conventional error correction methods are used, then error correction capability is achieved, but wiring complexity increases
Solution Approach 1:
The patent segments the memory into units where each data bit is associated with multiple check bits in a structured pattern. This segmentation creates a systematic wiring arrangement where lines connect data bits to their corresponding check bits without requiring complex intersecting connections, thereby reducing wiring complexity while maintaining error correction capability.
Solution Approach 2:
The patent organizes memory cells and their connections in a two-dimensional array structure with systematic addressing. By mapping the error correction relationships onto a spatial grid pattern, the wiring complexity is reduced as connections follow regular patterns rather than requiring complex routing in a single dimension.
3Reliability
If more memory cells are used for error correction, then error tolerance improves, but data density decreases
Solution Approach 1:
The patent implements error correction by assigning check bits locally to specific data bits rather than using global redundancy. Each data bit has its own dedicated check bits, and the correction logic operates locally on these associated pairs. This local quality approach provides robust error tolerance while minimizing the overhead ratio, thereby maintaining higher data density compared to global redundancy schemes.
Data Source
AI summary
In an embodiment, a storage device includes a multiplicity of data value memory cells and a multiplicity of check value memory cells, where at least one of the multiplicity of data value memory cells is assigned to two of the check value memory cells, and where at least one of the multiplicity of check value memory cells is assigned to two of the data value memory cells, and a correction circuit which is configured to output a corrected data value when reading out a selected data value memory cell of the at least one of the multiplicity of data value memory cells, based on a content of the selected data value memory cell and based on contents of the two check value memory cells assigned to the selected data value memory cell.