Memory Cell Error Detection with Oxide Semiconductor Transistors
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in preventing error bits, improving reliability, reducing delay time, and minimizing power consumption and area, particularly in multi-level data retention scenarios.
Innovation Solution
A memory device configuration that includes a memory cell with (N−1)-bit data and an error detection bit, utilizing an oxide semiconductor transistor to manage data states and threshold voltages, allowing for error detection and correction without reading the error detection bit during reading operations, thereby preventing error bits and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level data retention is implemented to increase storage capacity, then the quantity of stored data increases, but the possibility of errors increases and reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by proactively detecting potential error states (intermediate threshold voltages) before they manifest as actual data errors. The system performs error detection bit checks during writing operations and proactively corrects threshold voltage drifts before they cause data corruption, thereby maintaining high reliability in multi-level data retention.
Solution Approach 2:
The patent implements feedback mechanisms through error detection bits that continuously monitor the state of stored data. The system reads error detection bits to determine if correction is needed, and feeds this information back to the writing transistor to adjust threshold voltages, creating a closed-loop system that maintains data integrity despite multi-level storage challenges.
2Reliability
If error detection and correction mechanisms are added to prevent error bits, then reliability improves, but device complexity and area increase
Solution Approach 1:
The patent merges error detection and correction functionality directly into the memory cell structure by integrating error detection bits alongside data bits in the same memory cell. This consolidation eliminates the need for separate error checking circuits and reduces overall device complexity while maintaining high reliability.
Solution Approach 2:
The writing transistor serves multiple functions: it writes data bits, manages error detection bits, and performs threshold voltage correction. This multi-functionality reduces the need for dedicated correction circuits and simplifies the overall device architecture while providing robust error prevention capabilities.
3Measurement precision
If error detection bit reading is performed during reading operations, then error detection accuracy improves, but reading speed decreases and delay time increases
Solution Approach 1:
The patent applies partial action by selectively reading only error detection bits during reading operations rather than reading all data bits. The system determines whether to perform error detection based on the error detection bit value, avoiding unnecessary full reads and reducing delay time while maintaining detection accuracy when needed.
Solution Approach 2:
The patent extracts error detection functionality from the main data reading path by using separate error detection bits that can be checked independently. This separation allows the system to verify error status without interfering with the primary data read operation, minimizing impact on reading speed.
4Reliability
If oxide semiconductor transistor is used to manage threshold voltages and data states, then reliability and error prevention improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes parameter changes in the oxide semiconductor transistor, specifically exploiting the controllable threshold voltage characteristic. By adjusting the threshold voltage of the writing transistor, the system can actively manage data states and correct errors, achieving high reliability while the inherent properties of oxide semiconductor materials provide manufacturing tolerance.
Data Source
AI summary
A memory cell retains (N−1)-bit data (N is an integer of more than 1) and an error detection bit. The memory cell has 2N data states A_1 to A_2N. Error detection bits for the data states A_i (i is 1 and an even number more than or equal to 4 and less than or equal to 2N) among the 2N data states are assigned “1” (normal), and the error detection bits for the other data states are assigned “0” (abnormal). The memory cell is brought to have the state A_i by a writing operation. During a reading operation, the error detection bit is not read out from the memory cell. The error detection bit together with the (N−1)-bit data is read out for refresh. If the error detection bit is “0”, refresh for bringing the error detection bit back to data state with the error detection bit “1” is performed.