Semiconductor Memory Cell Etch Stop Structure for Layer Protection
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Solution Overview
Problem
Existing etching processes for manufacturing semiconductor memory arrays often damage or etch the charge-trapping layer and channel layer due to limitations in etchant selectivity and tool precision, leading to increased defects and reduced production yield.
Innovation Solution
The introduction of an additional etching stop layer provides enhanced protection for the charge-trapping layer and channel layer during etching operations, reducing damage and improving the manufacturing process by ensuring less defects and higher production yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional etching processes are used, then etching speed and productivity are maintained, but the charge-trapping layer and channel layer are damaged or etched, leading to increased defects
Solution Approach 1:
An etch stop layer is introduced as an intermediary between the filling layer and the charge-trapping layer. This stop layer selectively prevents the etchant from reaching and damaging the charge-trapping layer and channel layer, while allowing the etching process to proceed at normal speeds on the filling layer. The stop layer acts as a protective mediator that resolves the conflict between etching speed and etching precision.
2Device complexity
If conventional etching processes are used, then manufacturing complexity is kept simple, but production yield is reduced due to layer damage and defects
Solution Approach 1:
The etch stop layer is deposited in advance, before the etching of the filling layer begins. This preliminary protective action ensures that when the etching process subsequently occurs, the charge-trapping layer and channel layer are already protected, preventing damage and improving production yield without requiring complex process changes.
3Reliability
If etchant selectivity is improved to protect critical layers, then layer protection is enhanced, but etching speed and productivity decrease
Solution Approach 1:
The etching process is segmented into two distinct stages: first, the etch stop layer is etched at high speed with standard etchants; second, the filling layer is etched with controlled selectivity. This segmentation allows each stage to be optimized independently, maintaining high productivity in the first stage while ensuring layer protection in the second stage.
Data Source
AI summary
A method includes forming a plurality of memory cells, which includes a plurality of first conductive lines over a substrate, charge-trapping layers coupled to the conductive lines, channel layers arranged adjacent to the charge-trapping layers, and a plurality of first filling regions arranged between the channel layers; etching the first filling regions to form first trenches; depositing a liner over upper surfaces of the charge-trapping layers and the channel layers and sidewalls of the first trenches; forming second filling regions in the first trenches; patterning the second filling regions to form second trenches; depositing a partition region in each of the second trenches; and removing the liner to expose the charge-trapping layers and the channel layers.