Memory Cell Extended Channel Reduces Punch Through Leakage
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Solution Overview
Problem
Conventional non-volatile memory cell arrays face significant challenges with punch through leakage, leading to high power consumption and reliability issues, particularly as semiconductor devices continue to shrink in size.
Innovation Solution
The method involves creating an extended channel region by floating doped regions between the source and drain bias terminals, reducing electrical fields and thereby minimizing punch through leakage in unselected memory cells during programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high voltage is applied to the drain terminal during programming operation, then programming speed is improved, but punch through leakage current increases in unselected memory cells
Solution Approach 1:
A lightly-doped drain extension region is introduced as an intermediary structure between the heavily-doped drain terminal and the channel region. This intermediate region acts as a buffer that reduces the electric field intensity, thereby suppressing punch-through leakage current while allowing high voltage to be applied for fast programming operations.
Solution Approach 2:
The patent applies different doping concentrations to different regions: heavy doping at the drain terminal for low resistance contact, light doping in the drain extension region for field reduction, and appropriate doping in the channel for threshold control. This local variation in doping quality enables simultaneous achievement of fast programming and leakage suppression.
2Productivity
If device dimensions are reduced to increase integration density, then productivity is improved, but punch through leakage becomes more severe
Solution Approach 1:
Instead of merely scaling down lateral dimensions, the patent extends the solution into the vertical dimension by adding a drain extension region that protrudes into the channel area. This dimensional approach provides additional space for field management without further reducing the already-small lateral dimensions, enabling continued scaling while controlling leakage.
3Device complexity
If conventional memory cell structure is used, then device complexity is low, but power consumption is high due to leakage current
Solution Approach 1:
The drain region is segmented into two distinct parts: a heavily-doped drain terminal for electrical contact and a lightly-doped drain extension region for field control. This segmentation allows each part to perform its specific function optimally, reducing overall power consumption while maintaining structural simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces punch through leakage currents, enhancing the reliability and efficiency of non-volatile memory cell arrays by lowering electrical fields and minimizing power consumption.
Implementation Method 1
punch through leakage in unselected memory cells during programming operations
Data Source
AI summary
A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells.