Memory Cell Initialization Using External Low-Resistance Forming
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Solution Overview
Problem
Existing memory systems face challenges in performing stable initialization operations for memory cells with variable resistance elements, which can lead to instability and potential damage during the forming process due to high voltages required for switching elements from high to low resistance states.
Innovation Solution
A method is introduced where variable resistance elements are initialized into a low resistance state through an external initialization process distinct from read or write operations, ensuring uniformity and reducing the risk of damage by applying a smaller forming voltage, thereby stabilizing the memory system's operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is applied to switch switching elements from high resistance state to low resistance state during forming process, then the switching elements can be initialized, but the variable resistance elements may be damaged due to excessive voltage
Solution Approach 1:
The patent applies preliminary action by initializing the variable resistance elements to a low resistance state before performing the forming process on the switching elements. This ensures that when high voltage is applied during forming, the variable resistance elements are already in a safe state that prevents damage, while still allowing the switching elements to be properly formed.
Solution Approach 2:
The patent changes the resistance state parameter of the variable resistance elements from high to low before the forming process. This parameter change allows the system to withstand the high voltage required for forming without damaging the variable resistance elements, as their low resistance state provides a safer operating condition during the high-stress forming operation.
2Object-affected harmful factors
If variable resistance elements are initialized before forming process, then damage risk is reduced, but additional initialization process steps are required
Solution Approach 1:
The patent applies universality by using the same initialization circuit and control logic for both initializing variable resistance elements before forming and for normal read/write operations. This multi-functional approach allows the system to perform multiple functions (pre-initialization and operational initialization) using the same hardware infrastructure, thereby minimizing the increase in device complexity while achieving damage risk reduction.
3Object-generated harmful factors
If variable resistance elements are in high resistance state during forming, then they provide better isolation, but higher voltage is required which increases damage risk
Solution Approach 1:
The patent applies inversion by reversing the conventional approach: instead of keeping variable resistance elements in high resistance state during forming (which provides isolation but requires high voltage), the patent initializes them to low resistance state before forming. This inverted approach prioritizes damage prevention over isolation quality during the forming process, recognizing that the forming operation itself overrides the need for isolation at that specific moment.
Data Source
AI summary
According to one embodiment, a method for manufacturing a memory system that has memory cells with a variable resistance element and a switching element connected between a first wire and second wire, includes forming the variable resistance elements in the memory system in a low resistance state or a high resistance state, and then bringing each of the variable resistance elements into the low resistance state before performing either of a read operation or a write operation by performing an external initialization process that is different from the read operation and the write operation. In some examples, the variable resistance element can be a magnetoresistance type element and the external initialization process may be exposing the memory cells to an external magnetic field.