Memory Cell Data Retention via Fast Bit Upshifting
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Solution Overview
Problem
Data retention errors occur in semiconductor memory devices due to charge leakage or electron loss during programming operations, leading to widening of voltage distributions and shrinking of margins between voltage distributions, resulting in programming errors as the devices age.
Innovation Solution
Implementing a second verification voltage level after the memory cell passes the first verification, and applying a bit line voltage based on the comparison to upshift fast bits to the upper portion of the final voltage distribution, counteracting the downshifting effect caused by charge leakage or electron loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are programmed using conventional verification methods, then programming speed is maintained, but data retention reliability deteriorates due to charge leakage and electron loss
Solution Approach 1:
The patent applies preliminary action by performing an additional verification at an intermediate voltage level before the final verification. This intermediate check allows for early detection of fast bits that may be susceptible to charge leakage, enabling corrective upshift before the programming operation completes. By acting in advance on potentially problematic cells, the method prevents data retention errors without significantly impacting overall programming speed.
Solution Approach 2:
The patent implements feedback by using the result of the intermediate verification to determine whether to apply an upshift voltage. The verification circuit provides feedback information about the state of fast bits, and this feedback controls the application of corrective voltage. This closed-loop approach ensures that upshift is applied only when necessary, maintaining reliability while minimizing additional programming time.
2Reliability
If additional verification steps are added to counteract charge leakage, then data retention reliability improves, but programming time increases
Solution Approach 1:
The patent applies partial action by performing an intermediate verification at a specific voltage level rather than continuously monitoring throughout the entire programming operation. This selective verification at a critical intermediate point provides sufficient information to identify fast bits needing correction without the overhead of continuous verification. The approach balances reliability improvement with minimal impact on programming speed by applying corrective action only where and when needed.
Data Source
AI summary
The present disclosure provides for improving data retention reliability. During a programming operation associated with a memory cell, after the memory cell passes verification of a first verification voltage level, a second verification voltage level can be applied to the memory cell. Based on a comparison of the voltage in the memory cell with the second verification voltage level, a bit line voltage may be applied. Based on the applied bit line voltage, fast bits associated with the memory cell can be upshifted to an upper portion of a final voltage distribution associated with the programming operation. Upshifting the fast bits counteracts the downshifting effect in a final voltage distribution that may be caused by charge leakage or electron loss.