Non-Volatile Memory Cell Refresh via Fatigue Monitoring
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Solution Overview
Problem
Traditional solid-state memory devices face inefficiencies in programming and reading operations due to their binary nature, which becomes increasingly troublesome as more bits are stored on each multi-level cell, leading to longer operation times and susceptibility to fatigue conditions.
Innovation Solution
The memory devices utilize threshold voltage ranges to represent multiple data values, allowing for single read and write operations that return complete bit patterns, rather than discrete bits, and include sample and hold circuitry to manage analog voltage signals, enabling efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If binary read/write operations are used in traditional solid-state memory devices, then the operation simplicity is maintained, but the operation time increases and productivity decreases when storing multiple bits per cell
Solution Approach 1:
The patent segments the data storage and retrieval process by implementing separate read and write operations that can independently access and manipulate multiple bits within a single memory cell. This allows parallel processing of multiple bits without requiring sequential binary operations, thereby improving operation speed while maintaining manageable complexity through structured segmentation of the memory array and control logic
Solution Approach 2:
The patent transitions from traditional binary (0-dimension) read/write operations to multi-bit operations by adding dimensional complexity to the data representation. Each memory cell stores multiple bits simultaneously, and the read/write operations access these bits in parallel across multiple voltage levels and current states, effectively moving from a scalar binary system to a multi-dimensional data space that improves productivity
2Quantity of substance
If multi-level cells with multiple bits per cell are implemented, then storage density increases, but susceptibility to fatigue conditions and errors increases
Solution Approach 1:
The patent implements feedback mechanisms through separate read operations that can detect fatigue conditions and error states in multi-level memory cells. The read operation measures current flow at different voltage levels to determine the state of multiple bits, and this feedback information is used to identify and correct fatigue-related degradation, thereby maintaining reliability while preserving high storage capacity
Solution Approach 2:
The patent applies preliminary action by performing read operations to detect and assess fatigue conditions before they lead to data corruption. The system proactively monitors the state of memory cells storing multiple bits, identifying early signs of fatigue through current measurements at various voltage levels, and can initiate corrective actions such as data refresh or error correction before reliability deteriorates
3Loss of time
If threshold voltage ranges are used to represent multiple data values, then operation time is reduced, but measurement precision requirements increase
Solution Approach 1:
The patent applies partial action by implementing read operations that measure current flow at specific, strategically chosen voltage levels rather than requiring exhaustive measurement across the entire threshold voltage range. The read operation samples current at discrete voltage points that are sufficient to determine the state of multiple bits, reducing measurement time while maintaining adequate precision through selective sampling of the voltage spectrum
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces operation times by handling multiple bits per cell with a single operation and enhances reliability by addressing fatigue conditions through data refreshing methods.
Implementation Method 1
The memory devices utilize threshold voltage ranges to represent multiple data values, allowing for single read and write operations that return complete bit patterns
Implementation Method 2
include sample and hold circuitry to manage analog voltage signals, enabling efficient data storage and retrieval
Data Source
AI summary
In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.