Memory Cell Arrangement With Fowler-Nordheim Erase
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Solution Overview
Problem
Conventional flash memory cells, such as the SST ESF-1 cell, face challenges with low endurance, high overlay accuracy requirements in lithography, and limited scalability due to large source underdiffusion, making them unsuitable for small memory sizes and high write/erase cycle stability.
Innovation Solution
The proposed memory cell arrangement incorporates a substrate with multiple doping wells and a control circuit that uses Fowler-Nordheim erase and source side injection mechanisms, along with a spacer select gate structure to optimize module area and endurance, allowing for efficient programming and erasing with reduced module area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If field enhanced poly/poly erase mechanism is used, then erase capability is achieved, but endurance deteriorates (10k-100k cycles)
Solution Approach 1:
The patent extracts the erase function from the poly/poly field enhanced mechanism and implements it through a separate control gate structure. The control gate is electrically isolated from the floating gate by an insulating layer, allowing independent voltage application for erase operations without relying on field enhanced mechanisms that limit endurance.
Solution Approach 2:
The patent introduces a control gate as an intermediary element between the floating gate and the external control circuitry. This control gate mediates the erase operation by applying voltages that enable electron tunneling through the insulating layer, replacing the direct field enhanced poly/poly mechanism and thereby improving endurance.
2Reliability
If split-gate concept is used, then erase function is achieved, but overlay accuracy requirements increase
Solution Approach 1:
The patent segments the gate structure into two distinct parts: a floating gate for charge storage and a control gate for voltage control. These are separated by an insulating layer, eliminating the need for precise overlay between poly layers while maintaining the split-gate erase function. The segmentation allows independent formation and alignment of each gate component.
Solution Approach 2:
The insulating layer acts as an intermediary between the floating gate and control gate, providing electrical isolation while allowing the two gates to be formed in separate lithography steps. This intermediary structure eliminates the stringent overlay requirements that would otherwise be necessary for direct poly/poly gate alignment.
3Ease of manufacture
If large source underdiffusion is used, then cell formation is achieved, but scalability deteriorates
Solution Approach 1:
The patent replaces the mechanical/diffusion-based cell formation mechanism with an electrically-controlled mechanism. Instead of relying on large source underdiffusion to define cell boundaries, the invention uses electrically isolated control gates and floating gates that can be precisely defined by deposition and etching processes, enabling better scalability to smaller dimensions.
4Ease of operation
If conventional flash cell structure is used, then basic memory function is achieved, but module area overhead increases
Solution Approach 1:
The patent merges the select transistor and storage cell functions into a more integrated structure. The control gate serves dual purposes: controlling the select transistor operation and enabling the erase function through voltage application, thereby reducing the overall module area compared to conventional separate structures.
Solution Approach 2:
The control gate structure is designed to perform multiple functions: it controls the select transistor, enables erase operations through voltage application, and works with the floating gate for charge storage. This multi-functionality reduces the number of separate components needed, thereby reducing module area overhead.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances endurance and scalability, achieving high write/erase stability and minimizing module area overhead, while avoiding the limitations of field enhanced poly/poly erase mechanisms and reducing alignment issues, thus improving retention after cycling performance.
Implementation Method 1
the control circuitry (650) may be configured to control the memory cell (600) such that charge carriers stored in the charge storing memory cell structure (610) are drained via at least the first doping well (631) by means of Fowler-Nordheim tunneling
Implementation Method 2
the control circuitry (650) may be configured to control the memory cell (600) such that charge carriers stored in the charge storing memory cell structure (610) are drained
Data Source
AI summary
In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.