Memory Cell Gate Layout for Stable Word-Line Voltage
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Solution Overview
Problem
The instability in writing or reading operations in semiconductor memory due to non-negligible power consumption and voltage variations caused by the length of word lines, as well as signal transmission abnormalities resulting from manufacturing defects in gate electrode lines, necessitates an optimization of the layout design of word lines.
Innovation Solution
The proposed solution involves a data storage cell design with a storage structure, two transistors, and resistors, where the first and second transistors have gates connected through a conductive line to equalize electric potential, and the storage structure is connected to a bit line and source line, with a reduced resistance in the conductive line to minimize voltage drop and line loading, thereby stabilizing signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the length of word lines is increased to connect more memory cells, then the coverage area increases, but power consumption increases and voltage stability deteriorates
Solution Approach 1:
The patent divides the word line into multiple separate gate electrode lines (first gate electrode line and second gate electrode line). Each gate electrode line connects to a subset of memory cell transistors, preventing the need for a single long word line. This segmentation reduces the length of each individual conductive line, thereby reducing power consumption and improving voltage stability while still covering the required memory area.
2Productivity
If multiple layers are disposed between gate and word line, then integration density increases, but electric potential equality between gates deteriorates
Solution Approach 1:
The patent implements equipotentiality by directly connecting the gates of corresponding memory cell transistors through conductive lines (first conductive line and second conductive line) that are specifically designed to have matched resistance values. This direct connection ensures that both gates maintain substantially equal electric potential, eliminating the potential differences that would otherwise arise from signal transmission through multiple intermediate layers.
3Adaptability or versatility
If gate electrode lines are used for signal transmission, then device functionality is achieved, but manufacturing defects cause signal transmission abnormalities
Solution Approach 1:
The patent implements redundancy by providing dual gate electrode lines (first and second gate electrode lines) that connect to the same memory cell transistors through different conductive paths. If one gate electrode line or its associated conductive line suffers from manufacturing defects or signal transmission abnormalities, the other line can still function to maintain device operation, thereby cushioning against the impact of manufacturing defects.
4Reliability
If conductive line resistance is reduced to minimize voltage drop, then voltage stability improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by making the conductive lines (first conductive line and second conductive line) with substantially equal resistance values, which are specifically optimized to be lower than the resistance of alternative path conductive lines. This localized optimization of conductive line resistance ensures minimal voltage drop and improved voltage stability at critical locations where gates need to maintain equal potential, without unnecessarily increasing the complexity of the entire interconnect structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability of semiconductor memory by equalizing electric potentials across gates and reducing voltage drops, leading to improved stability and efficiency in writing and reading operations, while avoiding signal transmission abnormalities caused by manufacturing defects.
Implementation Method 1
The first gate is electrically connected to the second gate through a first conductive line... a reduced resistance in the conductive line to minimize voltage drop and line loading, thereby stabilizing signal transmission
Data Source
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AI summary
The invention discloses a memory fabrication method. The memory fabrication method includes forming a plurality of gate electrode lines to respectively form a plurality of gates of a plurality of data storage cells, and forming a plurality of conductive lines. The plurality of data storage cells are arranged in an array. Each of the plurality of conductive lines is coupled to two of the plurality of gate electrode lines. Each of the plurality of conductive lines at least partially overlaps the two gate electrode lines of the plurality of gate electrode lines.